AD9775EB AD [Analog Devices], AD9775EB Datasheet - Page 14

• Manufacturer Part Number: AD9775EB
• Description: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
• Manufacturer: AD [Analog Devices]

AD9775
REGISTER DESCRIPTION
Address 00h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Address 01h
Bits 7, 6
Bits 5, 4
Logic “0” (default). Causes the SDIO pin to act as
an input during the data transfer (Phase 2) of the
communications cycle. When set to “1,” SDIO
can act as an input or output, depending on Bit 7 of
the instruction byte.
Logic “0” (default). Determines the direction
(LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the section
MSB/LSB Transfers for a detailed description.
Writing a “1” to this bit resets the registers to their
default values and restarts the chip. The RESET bit
always reads back “0.” Register Address 00h bits are
not cleared by this software reset. However, a high
level at the RESET pin forces all registers, including
those in Address 00h, to their default state.
Sleep Mode. A Logic “1” to this bit shuts down the
DAC output currents.
Power-Down. Logic “1” shuts down all analog and
digital functions except for the SPI port.
1R/2R Mode. The default (“0”) places the AD9775
in two resistor mode. In this mode, the I
for the I and Q DAC references are set separately by
the R
59 and 60). In the 2R mode, assuming the coarse
gain setting is full scale and the fine gain setting is
zero, I
I
to “1,” the reference currents for both I and Q
DACs are controlled by a single resistor on Pin 60.
I
and Q DACs is half of what it would be in the 2R
mode, assuming all other conditions (R
settings) remain unchanged. The full-scale current
of each DAC can still be set to 20 mA by choosing
a resistor of half the value of the R
the 2R mode.
PLL_LOCK Indicator. When the PLL is enabled,
reading this bit will give the status of the PLL. A
Logic “1” indicates the PLL is locked. A Logic “0”
indicates an unlocked state.
Filter interpolation rate according to the follow-
ing table:
00
01
10
11
Modulation mode according to the following table:
00
01
10
11
FULLSCALE2
FULLSCALE
SET
FULLSCALE1
1×
2×
4×
8×
none
f
f
f
resistors on FSADJ1 and FSADJ2 (Pins
S
S
S
/2
/4
/8
in one resistor mode for both of the I
= 32 × V
= 32 × V
REF
/FSADJ2. With this bit set
REF
/FSADJ1 and
SET
value used in
SET
REF
, register
currents
–14–
Bit 3
Bit 2
Bit 1
Bit 0
Address 02h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 2
Bit 1
Bit 0
Logic “1” enables zero stuffing mode for interpo-
lation filters.
Default (“1”) enables the real mix mode. The I and
Q data channels are individually modulated by f
f
complex modulation is done. In the complex mix
mode (Logic “0”), the digital modulators on the I
and Q data channels are coupled to create a digi-
tal complex modulator. When the AD9775 is
applied in conjunction with an external quadrature
modulator, rejection can be achieved of either the
higher or lower frequency image around the second
IF frequency (i.e., the second IF frequency is the
LO of the analog quadrature modulator external to
the AD9775) according to the bit value of Register
01h, Bit 1.
Logic “0” (default) causes the complex modulation
to be of the form e
the higher frequency image when the AD9775 is used
with an external quadrature modulator. A Logic “1”
causes the modulation to be of the form e
causes rejection of the lower frequency image.
In two port mode, a Logic “0” (default) causes Pin 8
to act as a lock indicator for the internal PLL. A
Logic “1” in this register causes Pin 8 to act as a
DATACLK, either generating or acting as an input
clock (see Register 02h, Bit 3) at the input data rate
of the AD9775.
Logic “0” (default) causes data to be accepted on
the inputs as two’s complement binary. Logic “1”
causes data to be accepted as straight binary.
Logic “0” (default) places the AD9775 in two port
mode. I and Q data enters the AD9775 via Ports 1
and 2, respectively. A Logic “1” places the AD9775
in one port mode in which interleaved I and Q data
is applied to Port 1. See the Pin Function Descrip-
tions for DATACLK/PLL_LOCK, IQSEL, and
ONEPORTCLK for detailed information on how
to use these modes.
DATACLK Driver Strength. With the internal PLL
disabled, and this bit set to Logic “0,” it is recom-
mended that DATACLK be buffered. When this bit
is set to Logic “1,” DATACLK acts as a stronger
driver capable of driving small capacitive loads.
Default Logic “0.” A value of “1” inverts DATACLK
at Pin 8.
Default Logic “0.” A value of 1 inverts
ONEPORTCLK at Pin 32.
The default of Logic “0” causes IQSEL = 1 to
direct input data to the I channel, while IQSEL = 0
directs input data to the Q channel. A Logic “1” in
this register inverts the sense of IQSEL.
The default of Logic “0” defines IQ pairing as IQ,
IQ...while programming a Logic “1” causes the pair
ordering to be QI, QI...
S
/4, or f
S
/8 after the interpolation filters. However, no
–j t
, resulting in the rejection of
+j t
, which
REV. 0
S
/2,