AD7366_07 AD [Analog Devices], AD7366_07 Datasheet - Page 7

• Manufacturer Part Number: AD7366_07
• Description: True Bipolar Input, Dual 1 ?s, 12-/14-Bit, 2-Channel SAR ADCs
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
AV
otherwise noted.
Table 4.
Parameter
t
f
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with t
The time required for the output to cross is 0.4 V or 2.4 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section and Figure 25.
2
CC
= DV
CC
= 4.75 V to 5.25 V, V
2.7 V ≤ V
680
610
10
35
30
10
40
0
10
20
7
0.3 × t
0.3 × t
10
70
1
SCLK
SCLK
DRIVE
< 4.75 V
Limit at T
DD
= 11.5 V to 16.5 V, V
MIN
4.75 V ≤ V
680
610
10
48
30
10
40
0
10
14
7
0.3 × t
0.3 × t
10
70
, T
MAX
SCLK
SCLK
DRIVE
≤ 5.25 V
SS
= −16.5 V to −11.5 V, V
Rev. 0 | Page 7 of 28
Unit
ns max
ns max
kHz min
MHz max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
μs
R
= t
Test Conditions/Comments
Conversion time, internal clock. CONVST falling edge to
BUSY falling edge
For the AD7367
For the AD7366
Frequency of serial read clock
Minimum quiet time required between the end of serial
read and the start of the next conversion
Minimum CONVST low pulse
CONVST falling edge to BUSY rising edge
BUSY falling edge to MSB valid once CS is low for t
BUSY going low
Delay from CS falling edge until Pin 1 (D
(D
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK low pulse width
SCLK high pulse width
CS rising edge to D
Power up time from shutdown mode; time required
between CONVST rising edge and CONVST falling edge
F
OUT
= 5 ns (10% to 90% of V
DRIVE
B) are three-state disabled
= 2.7 V to 5.25 V, T
OUT
A, D
DRIVE
) and timed from a voltage level of 1.6 V.
OUT
A
B, high impedance
= T
AD7366/AD7367
MIN
to T
OUT
MAX
A) and Pin 23
, unless
4
prior to