AD7366_07 AD [Analog Devices], AD7366_07 Datasheet - Page 22

• Manufacturer Part Number: AD7366_07
• Description: True Bipolar Input, Dual 1 ?s, 12-/14-Bit, 2-Channel SAR ADCs
• Manufacturer: AD [Analog Devices]

AD7366/AD7367
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram
for serial interfacing to the AD7366 and the AD7367. On the
falling edge of
converts the selected channels. These conversions are performed
using the on-chip oscillator. After the falling edge of
the BUSY signal goes high, indicating the conversion has started.
It returns low once the conversion has been completed. The data
can now be read from the
CS and SCLK signals are required to transfer data from the
AD7366/AD7367. The AD7366/AD7367 have two output pins
corresponding to each ADC. Data can be read from the AD7366/
AD7367 using both D
output pin of the user’s choice can be used. The SCLK input
signal provides the clock source for the serial interface. The CS
goes low to access data from the AD7366/AD7367. The falling
edge of CS takes the bus out of three-state and clocks out the
MSB of the conversion result. The data stream consists of
12 bits of data for the AD7366 and 14 bits of data for the
AD7367, MSB first. The first bit of the conversion result is
valid on the first SCLK falling edge after the CS falling edge.
The subsequent 11-/13-bits of data for the AD7366/AD7367
respectively are clocked out on the falling edge of the SCLK
signal. A minimum of 12 clock pulses must be provided to
AD7366 to access each conversion result, while a minimum
of 14 clock pulses must be provided to AD7367 to access the
conversion result. Figure 25 shows how a 12 SCLK read is used
to access the conversion results while Figure 26 illustrates the
case for the AD7367 with a 14 SCLK read.
D
D
D
D
SCLK
OUT
OUT
SCLK
OUT
OUT
CS
CS
A
B
A
B THREE-
THREE-
STATE
STATE
CNVST
OUT
DB11
DB13
the AD7366/AD7367 simultaneously
A and D
1
1
D
t
t
4
4
DB10
DB12
OUT
pins.
OUT
2
2
DB11
B. Alternatively, a single
DB9
3
3
DB10
Figure 25. Serial Interface Timing Diagram for the AD7366
Figure 26. Serial Interface Timing Diagram for the AD7367
DB8
4
4
CNVST
t
t
5
5
t
t
8
8
5
5
Rev. 0 | Page 22 of 28
t
t
6
6
On the rising edge of CS , the conversion is terminated and
D
high, but is instead held low for a further 12 SCLK cycles for the
AD7366 or 14 SCLK cycles for the AD7367, on either D
D
This is illustrated in Figure 27
D
three-state on the rising edge of CS .
If the falling edge of SCLK coincides with the falling edge of
CS , then the falling edge of SCLK is not acknowledged by the
AD7366/AD7367, and the next falling edge of the SCLK is the
first registered after the falling edges of the CS .
The CS pin can be brought low before the BUSY signal goes
low indicating the end of a conversion. Once CS is at a logic low
state the data bus is brought out of three-state. This feature can
be utilized to ensure that the MSB is valid on the falling edge of
BUSY by bring CS low a minimum of t
BUSY signal goes low. The dotted
Figure 23 illustrates this.
Alternatively, the CS pin can be tied to a low logic state continu-
ously. Now the D
bus is continuously active. Under these conditions, the MSB of
the conversion result for the AD7366/AD7367 is available on
the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
OUT
OUT
OUT
A and D
B, the data from the other ADC follows on the D
A is shown. In this case, the D
t
DB2
t
DB2
7
7
OUT
DB1
DB1
B go back into three-state. If CS is not brought
OUT
pins never enter three-state and the data
DB0
DB0
t
t
9
9
14
12
and
CS line
THREE-STATE
Figure 28 where the case for
THREE-STATE
OUT
line in use goes back into
4
nanoseconds before the
in Figure 22 and
OUT
OUT
pin.
A or