M48TMH1 STMICROELECTRONICS [STMicroelectronics], M48TMH1 Datasheet - Page 9

• Manufacturer Part Number: M48TMH1
• Description: 5V PC REAL TIME CLOCK
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Table 9. AC Characteristics
(T
Note: 1. See Table 10.
When an interrupt event occurs, the related flag bit
(Register C; Bit 6 = PF; Bit 5 = AF; Bit 4 = UF) is
set to a logic "1". These flag bits are set indepen-
dent of the state of the corresponding enable bit in
Register B and can be used in a polling mode with-
out enabling the corresponding enable bits. The
interrupt flag bits are status bits which software
can interrogate as necessary.
When a flag is set, an indication is given to soft-
ware that an interrupt event has occurred since the
flag bit was last read; however, care should be tak-
en when using the flag bits as all are cleared each
time Register C is read. Double latching is includ-
ed with Register C so that bits which are set, re-
main stable throughout the read cycle. All bits
which are set high are cleared when read. Any
new interrupts which are pending during the read
cycle are held until after the cycle is completed.
A
Symbol
= 0 to 70 °C; V
t
t
t
t
t
t
t
t
t
t
t
t
PI
RWH
DHW
RWS
DHR
ASW
t
t
CYC
DSH
t
t
t
t
DAS
ASD
BUC
t
DSL
DW
OD
CS
CH
AS
AH
UC
(1)
Cycle Time
Pulse Width, Data Strobe Low or R/W High
Pulse Width, Data Strobe High or R/W Low
R/W Hold Time
R/W Setup Time
Chip Select Setup Time
Chip Select Hold Time
Read Data Hold Time
Write Data Hold Time
Address Setup Time
Address Hold Time
Delay Time, Data Strobe to Address Strobe Rise
Pulse Width Address Strobe High
Delay Time, Address Strobe to Data Strobe Rise
Output Data Delay Time from Data Strobe Rise
Write Setup Time
Delay Time before Update Cycle
Periodic Interrupt Time interval
Time of Update Cycle
CC
= 4.5V to 5.5V)
Parameter
One, two, or three bits can be set when reading
Register C. Each utilized flag bit should be exam-
ined when read to ensure that no interrupts are
lost.
The second flag bit usage method is with fully en-
abled interrupts. When an interrupt flag bit is set
and the corresponding enable bit is also set, the
IRQ pin is asserted low. IRQ is asserted as long as
at least one of the three interrupt sources has its
flag and enable bits both set. The IRQF bit (Regis-
ter C; Bit 7) is a "1" whenever the IRQ pin is being
driven low. Determination that the RTC initiated an
interrupt is accomplished by reading Register C.A
logic "1" in the IRQF bit indicates that one or more
interrupts have been initiated by the M48T86. The
act of reading Register C clears all active flag bits
and the IRQF bit.
Min
160
80
55
10
20
10
30
35
30
0
5
0
0
0
5
–
M48T86
Typ
244
–
1
Max
25
50
–
M48T86
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
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