M48TMH1 STMICROELECTRONICS [STMicroelectronics], M48TMH1 Datasheet - Page 16

• Manufacturer Part Number: M48TMH1
• Description: 5V PC REAL TIME CLOCK
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M48T86
REGISTER B
MSB
SET
When the SET bit is a zero, the update transfer
functions normally by advancing the counts once
per second. When the SET bit is written to a one,
any update transfer is inhibited and the program
may initialize the time and calendar bytes without
an update occurring. Read cycles can be executed
in a similar manner. SET is a read/write bit which
is not modified by RST or internal functions of the
M48T86.
PIE. Periodic Interrupt Enable
The Periodic Interrupt Enable bit (PIE) is a read/
write bit which allows the Periodic Interrupt Flag
(PF) bit Register C to cause the IRQ pin to be driv-
en low. When the PIE bit is set to one, periodic in-
terrupts are generated by driving the IRQ pin low
at a rate specified by the RS3-RS0 bits of Register
A. A zero in the PIE bit blocks the IRQ output from
being driven by a periodic interrupt, but the Period-
ic Flag (PF) bit is still set at the periodic rate. PIE
is not modified by any internal M48T86 functions,
but is cleared to zero on RST.
AIE. Alarm Interrupt Enable
The Alarm Interrupt Enable (AIE) bit is a Read/
Write bit which, when set to a one, permits the
Alarm Flag (AF) bit in Register C to assert IRQ. An
alarm interrupt occurs for each second that the
three time bytes equal the three alarm bytes in-
cluding a "don’t care" alarm code of binary
1XXXXXXX. When the AIE bit is set to zero, the
AF bit does not initiate the IRQ signal. The RST
pin clears AIE to zero. The internal functions of the
M48T86 do not affect the AIE bit.
UIE. Update Ended Interrupt Enable
The Update Ended Interrupt Enable (UIE) bit is a
read/write bit which enables the Update End Flag
(UF) bit in Register C to assert IRQ. A transition
low on the RST pin or the SET bit going high clears
the UIE bit.
16/23
BIT7
SET
BIT6
PIE
BIT5
AIE
BIT4
UIE
SQWE. Square Wave Enable
When the Square Wave Enable (SQWE) bit is set
to a one, a square wave signal is driven out on the
SQW pin. The frequency is determined by the
rate-selection bits RS3-RS0. When the SQWE bit
is set to zero, the SQW pin is held low. The SQWE
bit is cleared by the RST pin. SQWE is a read/write
bit.
DM. Data Mode
The Data Mode (DM) bit indicates whether time
and calendar information are in binary or BCD for-
mat. The DM bit is set by the program to the appro-
priate format and can be read as required. This bit
is not modified by internal function or RST. A one
in DM signifies binary data and a zero specifies Bi-
nary Coded Decimal (BCD) data.
24/12
The 24/12 control bit establishes the format of the
hours byte.A one indicates the 24-hour mode and
a zero indicates the 12-hour mode. This bit is read/
write and is not affected by internal functions or
RST.
DSE. Daylight Savings Enable
The Daylight Savings Enable (DSE) bit is a read/
write bit which enables two special updates when
set to a one. On the first Sunday in April, the time
increments from 1:59:59AM to 3:00:00 AM. On the
last Sunday in October, when the time reaches
1:59:59 AM, it changes to 1:00:00 AM. These spe-
cial updates do not occur when the DSE bit is a ze-
ro. This bit is not affected by internal functions or
RST.
SQWE
BIT3
BIT2
DM
24/12
BIT1
BIT0
DSE