DS152 XILINX [Xilinx, Inc], DS152 Datasheet - Page 41

• Manufacturer Part Number: DS152
• Description: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Table 57: DSP48E1 Switching Characteristics (Cont’d)
DS152 (v2.10) October18, 2010
Advance Product Specification
Setup and Hold Times of Data Pins to the Pipeline Register Clock
T
T
T
Setup and Hold Times of Data/Control Pins to the Output Register Clock
T
T
T
T
T
T
T
T
T
Setup and Hold Times of the CE Pins
T
T
T
T
T
T
Setup and Hold Times of the RST Pins
T
T
T
T
T
T
Combinatorial Delays from Input Pins to Output Pins
T
T
T
T
DSPDCK_{A, ACIN, B, BCIN}_MREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_MREG_MULT
DSPDCK_{A, D}_ADREG
DSPDCK_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
DSPCKD_{PCIN, CARRYCASCIN, MULTSIGNIN}_PREG
DSPDO_{A, B}_{P, CARRYOUT}_MULT
DSPDO_D_{P, CARRYOUT}_MULT
DSPDO_{A, B}_{P, CARRYOUT}
DSPDO_{C, CARRYIN}_{P, CARRYOUT}
DSPDCK_{A, ACIN, B, BCIN}_PREG_MULT
DSPCKD_{A, ACIN, B, BCIN}_PREG_MULT
DSPDCK_D_PREG_MULT
DSPCKD_D_PREG_MULT
DSPDCK_{A, ACIN, B, BCIN}_PREG
DSPCKD_{A, ACIN, B, BCIN}_PREG
DSPDCK_C_PREG
DSPDCK_{CEA; CEB}_{AREG; BREG}
DSPCKD_{CEA; CEB}_{AREG; BREG}
DSPDCK_CEC_CREG
DSPDCK_CED_DREG
DSPDCK_CEM_MREG
DSPDCK_CEP_PREG
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
DSPDCK_RSTC_CREG
DSPDCK_RSTD_DREG
DSPDCK_RSTM_MREG
DSPDCK_RSTP_PREG
/ T
Symbol
/ T
/ T
DSPCKD_C_PREG
/ T
/ T
/ T
/ T
/ T
/ T
/ T
DSPCKD_{A, D}_ADREG
DSPCKD_CEP_PREG
DSPCKD_CEC_CREG
DSPCKD_CED_DREG
/
DSPCKD_CEM_MREG
DSPCKD_RSTP_PREG
DSPCKD_RSTC_CREG
DSPCKD_RSTD_DREG
DSPCKD_RSTM_MREG
/
/
/
/
/
/
{A, ACIN, B, BCIN} input to M register
CLK
{A, D} input to AD register CLK
{A, ACIN, B, BCIN} input to P register
CLK using multiplier
D input to P register CLK
{A, ACIN, B, BCIN} input to P register
CLK not using multiplier
C input to P register CLK
{PCIN, CARRYCASCIN, MULTSIGNIN}
input to P register CLK
{CEA; CEB} input to {A; B} register CLK
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
{RSTA, RSTB} input to {A, B} register
CLK
RSTC input to C register CLK
RSTD input to D register CLK
RSTM input to M register CLK
RSTP input to P register CLK
{A, B} input to {P, CARRYOUT} output
using multiplier
D input to {P, CARRYOUT} output using
multiplier
{A, B} input to {P, CARRYOUT} output
not using multiplier
{C, CARRYIN} input to {P, CARRYOUT}
output
www.xilinx.com
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Description
–0.13
–0.47
–0.13
–0.10
–0.02
2.36/
1.24/
3.83/
3.62/
1.59/
1.42/
1.23/
0.14/
0.15/
0.20/
0.16/
0.32/
0.27/
0.18/
0.28/
0.20/
0.26/
0.04
0.10
0.19
0.18
0.12
0.19
0.02
0.17
0.08
0.15
0.24
0.04
3.76
3.57
1.55
1.38
-3
–0.13
–0.47
–0.13
–0.10
–0.02
2.70/
1.42/
4.37/
4.13/
1.81/
1.61/
1.41/
0.17/
0.18/
0.24/
0.20/
0.38/
0.31/
0.20/
0.32/
0.23/
0.30/
0.04
0.12
0.22
0.20
0.13
0.21
0.02
0.19
0.08
0.16
0.26
0.04
4.29
4.07
1.76
1.56
-2
Speed
–0.13
–0.47
–0.13
–0.10
–0.02
3.21/
1.69/
5.20/
4.90/
2.15/
1.91/
1.67/
0.22/
0.24/
0.31/
0.26/
0.46/
0.38/
0.23/
0.38/
0.26/
0.35/
0.04
0.13
0.25
0.23
0.14
0.25
0.03
0.22
0.09
0.19
0.30
0.05
5.08
4.82
2.07
1.83
-1
–0.24
–0.77
–0.24
–0.19
–0.07
3.66/
1.91/
5.94/
5.61/
2.44/
2.16/
1.91/
0.30/
0.31/
0.43/
0.32/
0.54/
0.41/
0.27/
0.45/
0.29/
0.43/
0.02
0.16
0.28
0.26
0.16
0.28
0.04
0.25
0.11
0.21
0.34
0.06
5.87
5.57
2.41
2.13
-1L
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
41