DS152 XILINX [Xilinx, Inc], DS152 Datasheet - Page 25

• Manufacturer Part Number: DS152
• Description: Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
• Manufacturer: XILINX [Xilinx, Inc]

Production Silicon and ISE Software Status
In some cases, a particular family member (and speed
grade) is released to production before a speed
specification is released with the correct label (Advance,
Preliminary, Production). Any labeling discrepancies are
corrected in subsequent speed specification releases.
Table 43: Virtex-6 Device Production Software and Speed Specification Release
IOB Pad Input/Output/3-State Switching Characteristics
Table 44
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
T
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
Table 44: IOB Switching Characteristics
DS152 (v2.10) October18, 2010
Advance Product Specification
Notes:
1.
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
LVDS_25
LVDSEXT_25
HT_25
IOPI
IOOP
Blank entries indicate a device and/or speed grade in advance or preliminary status.
is described as the delay from IOB pad through the
Device
is described as the delay from the O pin to the IOB
summarizes the values of standard-specific data
I/O Standard
ISE 12.1 v1.06
ISE 12.1 v1.06
ISE 12.1 v1.06
ISE 12.2 v1.08
N/A
N/A
N/A
N/A
-3
0.85
0.85
0.85
-3
Speed Grade
0.94
0.94
0.94
-2
T
IOPI
ISE 11.4.1 v1.04
ISE 12.2 v1.08
ISE 11.5 v1.05
ISE 12.1 v1.06
ISE 12.2 v1.08
1.09
1.09
1.09
-1
www.xilinx.com
-2
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Speed Grade Designations
1.08
1.08
1.08
-1L
Table 43
member, speed grade, and the minimum corresponding
supported speed specification version and ISE software
revisions. The ISE® software and speed specifications
listed are the minimum releases required for production. All
subsequent releases of software and speed specifications
are valid.
T
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
Table 45
described as the delay from the T pin to the IOB pad
through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
ISE 12.2 v1.07
ISE 12.2 v1.08
ISE 12.1 v1.06
ISE 12.2 v1.08
1.45
1.53
1.51
IOTP
-3
is described as the delay from the T pin to the IOB
Speed Grade
1.54
1.65
1.62
-2
lists the production released Virtex-6 family
summarizes the value of T
T
IOOP
ISE 11.4.1 v1.04
ISE 11.5 v1.05
ISE 12.1 v1.06
1.68
1.84
1.78
-1
-1
1.62
1.73
1.69
-1L
1.45
1.53
1.51
-3
Speed Grade
1.54
1.65
1.62
-2
IOTPHZ
ISE 12.3 v1.07 Patch
ISE 12.3 v1.07 Patch
ISE 12.3 v1.07 Patch
ISE 12.3 v1.07 Patch
T
IOTP
ISE 12.2 v1.05
ISE 12.2 v1.04
ISE 12.2 v1.04
ISE 12.2 v1.04
ISE 12.2 v1.04
1.68
1.84
1.78
-1
. T
N/A
N/A
N/A
N/A
-1L
IOTPHZ
1.69
1.62
1.73
-1L
is
Units
ns
ns
ns
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