M48T201V-70MH1 STMICROELECTRONICS [STMicroelectronics], M48T201V-70MH1 Datasheet - Page 11

• Manufacturer Part Number: M48T201V-70MH1
• Description: 3.3V-5V TIMEKEEPER CONTROLLER
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

WRITE Mode
The M48T201Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable. The start
of a WRITE is referenced from the latter occurring
falling edge of W or E. A WRITE is terminated by
the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
must return high for a minimum of t
Enable or t
initiation of another READ or WRITE Cycle. Data-
in must be valid t
and remain valid for t
kept high during WRITE Cycles to avoid bus con-
Figure 7. WRITE Cycle Timing: RTC & External RAM Control Signals
ADDRESS
E
E CON
G
G CON
W
DQ0-DQ7
WHAX
DVWH
from WRITE Enable prior to the
tAVEL
DATA OUT
tAVWL
WHDX
VALID
prior to the end of WRITE
afterward. G should be
tRO
tEPD
tEHQZ
tAVEH
WRITE
tELEH
EHAX
tAVAV
tWLWH
tEPD
from Chip
DATA IN
VALID
tEHDX
tDVEH
tEHAX
tAVWH
tDVWH
WRITE
tention; although, if the output bus has been acti-
vated by a low on E and G a low on W will disable
the outputs t
When the address value presented to the
M48T201Y/V during the WRITE is in the range of
7FFFFh-7FFF0h, one of the on-board TIME-
KEEPER
be written into the device. When the address value
presented to M48T201Y/V is outside the range of
TIMEKEEPER registers, an external SRAM loca-
tion is selected.
tAVAV
tWHAX
®
DATA IN
VALID
registers will be selected and data will
WLQZ
tWHQX
after W falls.
tWHDX
tAVAV
READ
M48T201Y, M48T201V
tAVQV
tGLQV
DATA OUT
tWLQZ
VALID
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