PCA85232DA NXP [NXP Semiconductors], PCA85232DA Datasheet - Page 26

• Manufacturer Part Number: PCA85232DA
• Description: LCD driver for low multiplex rates
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
PCA85232
Product data sheet
7.17 Command decoder
The acknowledgement after each byte is made only by the (A0 and A1) addressed
PCA85232. After the last (display) byte, the I
Alternatively a START may be asserted to RESTART an I
The command decoder identifies command bytes that arrive on the I
commands available to the PCA85232 are defined in
Table 9.
Table 10.
[1]
[2]
[3]
Table 11.
[1]
Command
Bit
mode-set
load-data-pointer-MSB
load-data-pointer-LSB
device-select
bank-select
blink-select
frequency-prescaler
Bit
7 to 4
3
2
1 to 0
Bit
7 to 4
3 to 0
Power-on and reset value.
The possibility to disable the display allows implementation of blinking under external control; the enable bit
determines also whether the internal clock signal is available at the CLK pin (see
Not applicable for static drive mode.
Power-on and reset value.
Definition of PCA85232 commands
Mode-set command bit description
Load-data-pointer-MSB command bit description
Symbol
-
E
B
M[1:0]
Symbol
-
P[7:4]
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 8 December 2010
Operation code
7
1
0
0
1
1
1
1
Value
1100
0
1
0
1
01
10
11
00
Value
0000
0000
1001
[1]
[1]
[1]
[1]
6
1
0
1
1
1
1
1
to
5
0
0
1
1
1
1
0
Description
display status
LCD bias configuration
LCD drive mode selection
Description
P7 to P4 defines the first 4 (most significant) bits of
the data pointer that indicates one of the 160 display
RAM addresses
fixed value
fixed value
disabled (blank)
enabled
1
1
static; BP0
1:2 multiplex; BP0, BP1
1:3 multiplex; BP0, BP1, BP2
1:4 multiplex; BP0, BP1, BP2, BP3
⁄
⁄
3
2
bias
2
bias
4
0
0
0
0
1
1
0
C-bus master issues a STOP condition (P).
3
E
P[7:4]
P[3:0]
0
1
0
1
LCD driver for low multiplex rates
Table
[2]
2
2
B
0
0
AB
F[2:0]
C-bus access.
9.
[3]
1
M[1:0]
A[1:0]
I
BF[1:0]
PCA85232
2
Section
C-bus. The
0
O
© NXP B.V. 2010. All rights reserved.
7.5.1).
Reference
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
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