PCF2114AU/10 PHILIPS [NXP Semiconductors], PCF2114AU/10 Datasheet - Page 48
PCF2114AU/10
Manufacturer Part Number
PCF2114AU/10
Description
LCD controller/drivers
Manufacturer
PHILIPS [NXP Semiconductors]
Datasheet
1.PCF2114AU10.pdf
(64 pages)
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12 to 15
STEP
11
16
17
18
19
20
21
22
23
write data to DDRAM
write data to DDRAM
(optional I
(as step 8)
control byte
Return Home
control byte for read
I
slave address for read
read data: 8
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack
2
Co
Co
C START
X
0
0
1
0
0
0
RS
RS
1
1
0
0
1
1
X
2
C stop) I
R/W
R/W
X
0
0
0
0
1
1
SCL + master acknowledge; note 2
2
X
X
X
0
1
C start + slave address for write
0
1
I
2
C BYTE
X
X
X
1
0
0
0
0
0
X
0
X
1
X
X
X
X
0
1
1
0
X
X
X
0
1
0
1
Ack
Ack
1
1
1
1
1
1
0
PH_
PHILIPS_
PHILIPS_
PHILIPS_
PHILIPS
PHILIPS
PHILIPS
PHILIPS
PHILIPS
DISPLAY
Writes ‘H’.
Writes ‘S’.
Sets DDRAM address 0 in Address Counter. (also returns
shifted display to original position. DDRAM contents
unchanged). This instruction does not update the Data Register
DDRAM content will be read from following instructions.
The R/W has to be set to 1 while still in I
During the acknowledge cycle the content of the DR is loaded
into the internal I
instruction neither a ‘Set address’ nor a ‘Read data’ has been
performed. Therefore the content of the DR was unknown.
8
acknowledge cycle is shifted out over SDA. MSB is DB7. During
master acknowledge content of DDRAM address 01 is loaded
into the I
SCL; content loaded into interface during previous
2
C interface.
2
C interface to be shifted out. In the previous
OPERATION
2
C-write mode.
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