HSP43168/883 INTERSIL [Intersil Corporation], HSP43168/883 Datasheet - Page 3

• Manufacturer Part Number: HSP43168/883
• Description: Dual FIR Filter
• Manufacturer: INTERSIL [Intersil Corporation]

Pin Description
CSEL0-4
OUT9-27
SHFTEN
MUX0-1
ACCEN
CIN0-9
INA0-9
INB0-9
FWRD
NAME
RVRS
TXFR
GND
A0-8
OEH
OEL
V
CLK
WR
CC
F9-11, G9-11, H10-11,
J10-11, J7, K11, K8-9,
E1-3, D1, C1-2, B1-3,
B5, D11, K10, K7, F1
K1, J1-2, H1-2, G1-3,
A9, E10, L11, K4, D2
L1-5, K2-3, K5-6, J5
A5-8, B6-8, C6-7
A2-4, B4, C5
NUMBER
L6-10
B9-10
F2-3
C10
C11
D10
A10
B11
A11
E11
PIN
A1
E9
J6
3
TYPE
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
V
Ground.
Control/Coefficient Data Bus. Processor interface for loading control data and coefficients.
CIN0 is the LSB.
Control/Coefficient Address Bus. Processor interface for addressing control and Coefficient
Registers. A0 is the LSB.
Control/Coefficient Write Clock. Data is latched into the Control and Coefficient Registers on
the rising edge of WR.
Coefficient Select. This input determines which of the 32 coefficient sets are to be used by
FIR A and B. This input is registered and CSEL0 is the LSB.
Input to FIR A. INA0 is the LSB.
Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output,
INB1-9 is the LSB’s of the output bus.
19 MSB’s of Output Bus. Data format is either unsigned or two’s complement depending on
configuration. OUT27 is the MSB.
Shift Enable. This active low input enables shifting of data through the Decimation Registers.
Forward ALU Input Enable. When active low, data from the forward decimation path is input
to the ALU’s through the “a” input. When high, the “a” inputs to the ALUs are zeroed.
Reverse ALU Input Enable. When active low, data from the reverse decimation path is input
to the ALU’s through the “b” input. When high, the “b” inputs to the ALUs are zeroed.
Data Transfer Control. This active low input switches the LIFO being read into the reverse
decimation path with the LIFO being written from the forward decimation path (see Figure 1).
Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 3.0
lists the various configurations.
Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR)
and the output enables (OEL, OEH) are registered by the rising edge of CLK.
Output Enable Low. This tristate control enables the LSB’s of the output bus to
INB1-9 when OEL is low.
Output Enable High. This tristate control enables OUT9-27 when OEH is low.
Accumulate Enable. This active high input allows accumulation in the FIR Cell Accumulator.
A low on this input latches the FIR Accumulator contents into the Output Holding Registers
while zeroing the feedback path in the accumulator.
CC
: +5V power supply pin.
HSP43168/883
DESCRIPTION