CAT9554 CATALYST [Catalyst Semiconductor], CAT9554 Datasheet - Page 6

• Manufacturer Part Number: CAT9554
• Description: 8-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT9554, CAT9554A
PIN DESCRIPTION
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device. The SCL line requires a pull-up resistor
if it is driven by an open drain output.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs. A pull-up resistor
must be connected from SDA line to Vcc. The value of
the pull-up resistor, R
minimum and maximum values from Figure 2 and Figure
3 (see Note).
Note: According to the Fast Mode I
can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source
(Imax = 3mA) or a switched resistor circuit.
Doc. No. 25088, Rev. B
Figure 2. Minimum R
2.5
1.5
0.5
2
1
0
2
2.4 2.8 3.2 3.6
(I OL = 3mA @ V OLmax )
Supply Voltage
P
, can be calculated based on
V CC (V)
P
4
Value versus
4.4 4.8 5.2 5.6
2
C bus specification, for bus capacitance up to 200pF, the pull up device
6
A
These inputs are used for extended addressing capability.
The A
When hardwired, up to eight CAT9554/9554As may be
addressed on a single bus system. The levels on these
inputs are compared with corresponding bits, A
from the slave address byte.
I/O
Any of these pins may be configured as input or output.
The simplified schematic of I/O
Figure 4. When an I/O is configured as an input, the Q1
and Q2 output transistors are off creating a high
impedance input with a weak pull-up resistor (typical 100
kΩ). If the I/O pin is configured as an output, the push-
pull output stage is enabled. Care should be taken if an
external voltage is applied to an I/O pin configured as an
output due to the low impedance paths that exist between
the pin and either V
0
, A
0
to I/O
8.00
7.00
6.00
5.00
4.00
3.00
2.00
1.00
0.00
1
0
, A
, A
(Fast Mode I 2 C Bus / tr max = 300ns)
Figure 3. Maximum R
2
1
: Device Address Inputs
7
, A
: Input / Output Ports
50
2
pins should be hardwired to V
100
Bus Capacitance
CC
150
C BUS (pF)
or V
Characteristics subject to change without notice
200
SS
.
© 2006 by Catalyst Semiconductor, Inc.
P
250
0
Value versus
to I/O
300
7
350
is shown in
CC
400
2
, A
or V
1
, A
SS
0
.
,