CAT9554 CATALYST [Catalyst Semiconductor], CAT9554 Datasheet - Page 10

• Manufacturer Part Number: CAT9554
• Description: 8-bit I2C and SMBus I/O Port with Interrupt
• Manufacturer: CATALYST [Catalyst Semiconductor]

CAT9554, CAT9554A
The output port register sets the outgoing logic levels of
the I/O ports, defined as outputs by the configuration
register. Bit values in this register have no effect on I/O
pins defined as inputs. Reads from the output port
register reflect the value that is in the flip-flop controlling
the output, not the actual I/O pin value.
The polarity inversion register allows the user to invert
the polarity of the input port register data. If a bit in this
register is set (“1”) the corresponding input port data is
inverted. If a bit in the polarity inversion register is
cleared (“0”), the original input port polarity is retained.
The configuration register sets the directions of the
ports. Set the bit in the configuration register to enable
FROM PORT
Doc. No. 25088, Rev. B
WRITE TO
DATA OUT
WRITE TO
REGISTER
PORT
SDA
SDA
SCL
SCL
start condition
start condition
S
S
1
1
0
0
2
2
1
1
slave address
slave address
3
3
0
0
Figure 10. Write to Configuration or Polarity Inversion Register
4
4
0 A2
0 A2
5
5
acknowledge
acknowledge
A1
6
A1
6
from slave
from slave
A0
A0
7
7
R/W
Figure 9. Write to Output Port Register
R/W
0
8
0
8
9
A
9
A
0
0
0
0
command byte
0
command byte
0
acknowledge from slave
acknowledge from slave
0
0
10
0
0
the corresponding port pin as an input with a high
impedance output driver. If a bit in this register is cleared,
the corresponding port pin is enabled as an output. At
power-up, the I/Os are configured as inputs with a weak
pull-up resistor to V
Data is transmitted to the CAT9554/9554A registers
using the write mode shown in Figure 9 and Figure 10.
The CAT9554/9554A registers are read according to
the timing diagrams shown in Figure 11 and Figure 12.
Once a command byte has been sent, the register which
was addressed will continue to be accessed by reads
until a new command byte will be sent.
0
0
0
1 1/0
1
A
A
CC
.
data to register
acknowledge from slave
acknowledge from slave
data to port
DATA 1
Characteristics subject to change without notice
DATA 1
© 2006 by Catalyst Semiconductor, Inc.
t pv
A
A
stop
condition
stop
condition
DATA 1 VALID
P
P