CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 9

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

4.12.4
Endpoints 0 and 1 are the same for every configuration.
Endpoint 0 is the only CONTROL endpoint, and endpoint 1 can
be either BULK or INTERRUPT. The endpoint buffers can be
configured in any 1 of the 12 configurations shown in the
vertical columns. In full-speed, BULK mode uses only the first
64 bytes of each buffer, even though memory exists for the
allocation of the isochronous transfers in BULK mode the
unused endpoint buffer space is not available for other opera-
tions. An example endpoint configuration would be:
EP2—1023 double buffered; EP6—64 quad buffered (column
8).
4.12.5
Table 4-6. Default Alternate Settings
4.13
4.13.1
The FX1 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories, and
Notes:
Document #: 38-08039 Rev. *B
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
Alternate
4.
5.
Setting
“0” means “not implemented.”
“2×” means “double buffered.”
Endpoint Configurations
Default Alternate Settings
External FIFO Interface
Architecture
64 64
0 64 bulk
0
0 64 bulk
0 64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
0 64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
0 64 bulk in (2×) 64 int in (2×)
0 64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
EP0 IN&OUT
EP1 OUT
EP1 IN
1
EP2
EP4
EP8
EP6
64
64
64
64
64
64
64
64
64
64
64
1
64
64 int
64 int
EP4
EP6
EP2
64
64
64
64
64
64
64
64
64
64
64
2
2
EP2
EP4
EP6
1023
1023
64
64
[4, 5]
64
64
64
64
64
3
Figure 4-5. Endpoint Configuration
64
64 int
64 int
64 iso in (2×)
EP2
EP8
EP6
64
64
64
64
64
64
64
64
64
64
64
4
3
EP2
EP6
64
64
64
64
64
64
64
64
64
64
64
5
EP2
EP6
1023
1023
64
64
64
64
64
64
64
6
are controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described
in Section 4.12.2.
In operation, some of the eight RAM blocks fill or empty from
the SIE, while the others are connected to the I/O transfer
logic. The transfer logic takes two forms, the GPIF for internally
generated control signals, or the slave FIFO interface for
externally controlled transfers.
4.13.2
The FX1 endpoint FIFOS are implemented as eight physically
distinct 256x16 RAM blocks. The 8051/SIE can switch any of
the RAM blocks between two domains, the USB (SIE) domain
and the 8051-I/O Unit domain. This switching is done virtually
instantaneously, giving essentially zero transfer time between
“USB FIFOS” and “Slave FIFOS.” Since they are physically the
same memory, no bytes are actually transferred between
buffers.
EP2
EP8
EP6
1023
1023
64
64
64
64
64
64
64
7
Master/Slave Control Signals
EP2
1023
1023
EP6
64
64
64
64
64
64
64
8
EP2
1023
EP6
1023
1023
1023
64
64
64
9
EP2
EP6
EP8
64
64
64
64
64
64
64
64
64
64
64
10
EP2 EP2
1023
EP8
1023
1023
1023
64
64
64
64
64
CY7C64713/14
11
1023
1023
1023
1023
12
64
64
64
Page 9 of 50