CY7C64713 CYPRESS [Cypress Semiconductor], CY7C64713 Datasheet - Page 20

• Manufacturer Part Number: CY7C64713
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 5-1. FX1 Pin Definitions (continued)
Document #: 38-08039 Rev. *B
TQFP
128
111
112
113
114
115
69
70
71
66
67
98
4
5
6
7
8
9
TQFP
100
89
90
91
92
93
54
55
56
51
52
76
3
4
5
6
7
8
QFN
56
29
30
31
1
2
INT6
PE6 or
T2EX
PE7 or
GPIFADR8
RDY0 or
SLRD
RDY1 or
SLWR
RDY2
RDY3
RDY4
RDY5
PE3 or
RXD0OUT
PE4 or
RXD1OUT
PE5 or
CTL0 or
FLAGA
CTL1 or
FLAGB
CTL2 or
FLAGC
CTL3
CTL4
CTL5
Name
Type
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input
Input
Input
Input
Input
Input
O/Z
O/Z
O/Z
O/Z
Output
Output
Default
[8]
(PE3)
(PE4)
(PE5)
(PE6)
(PE7)
N/A
N/A
N/A
N/A
N/A
N/A
H
H
H
H
H
H
I
I
I
I
I
Multiplexed pin whose function is selected by the PORTECFG.3 bit.
PE3 is a bidirectional I/O port pin.
RXD0OUT is an active-HIGH signal from 8051 UART0. If RXD0OUT is
selected and UART0 is in Mode 0, this pin provides the output data for
UART0 only when it is in sync mode. Otherwise it is a 1.
Multiplexed pin whose function is selected by the PORTECFG.4 bit.
PE4 is a bidirectional I/O port pin.
RXD1OUT is an active-HIGH output from 8051 UART1. When RXD1OUT
is selected and UART1 is in Mode 0, this pin provides the output data for
UART1 only when it is in sync mode. In Modes 1, 2, and 3, this pin is HIGH.
Multiplexed pin whose function is selected by the PORTECFG.5 bit.
PE5 is a bidirectional I/O port pin.
INT6 is the 8051 INT6 interrupt request input signal. The INT6 pin is edge-
sensitive, active HIGH.
Multiplexed pin whose function is selected by the PORTECFG.6 bit.
PE6 is a bidirectional I/O port pin.
T2EX is an active-high input signal to the 8051 Timer2. T2EX reloads timer
2 on its falling edge. T2EX is active only if the EXEN2 bit is set in T2CON.
Multiplexed pin whose function is selected by the PORTECFG.7 bit.
PE7 is a bidirectional I/O port pin.
GPIFADR8 is a GPIF address output pin.
IFCONFIG[1..0].
RDY0 is a GPIF input signal.
SLRD is the input-only read strobe with programmable polarity (FIFOPIN-
POLAR.3) for the slave FIFOs connected to FD[7..0] or FD[15..0].
IFCONFIG[1..0].
RDY1 is a GPIF input signal.
SLWR is the input-only write strobe with programmable polarity (FIFOPIN-
POLAR.2) for the slave FIFOs connected to FD[7..0] or FD[15..0].
RDY2 is a GPIF input signal.
RDY3 is a GPIF input signal.
RDY4 is a GPIF input signal.
RDY5 is a GPIF input signal.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL0 is a GPIF control output.
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to programmable for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL1 is a GPIF control output.
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[1:0] pins.
Multiplexed pin whose function is selected by the following bits:
IFCONFIG[1..0].
CTL2 is a GPIF control output.
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[1:0] pins.
CTL3 is a GPIF control output.
CTL4 is a GPIF control output.
CTL5 is a GPIF control output.
Multiplexed pin whose function is selected by the following bits:
Multiplexed pin whose function is selected by the following bits:
Description
CY7C64713/14
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