ADF4157 AD [Analog Devices], ADF4157 Datasheet - Page 18

• Manufacturer Part Number: ADF4157
• Description: High Resolution 6 GHz Fractional-N Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4157
SPUR MECHANISMS
The fractional interpolator in the ADF4157 is a third-order Σ-Δ
modulator (SDM) with a 25-bit fixed modulus (MOD). The SDM
is clocked at the PFD reference rate (f
frequencies to be synthesized at a channel step resolution of
f
fractional-N synthesizers, and how they affect the ADF4157,
are discussed in this section.
Fractional Spurs
In most fractional synthesizers, fractional spurs can appear at
the set channel spacing of the synthesizer. In the ADF4157,
these spurs do not appear. The high value of the fixed modulus
in the ADF4157 makes the Σ-Δ modulator quantization error
spectrum look like broadband noise, effectively spreading
the fractional spurs into noise.
Integer Boundary Spurs
Interactions between the RF VCO frequency and the PFD
frequency can lead to spurs known as integer boundary spurs.
When these frequencies are not integer related (which is
the purpose of the fractional-N synthesizer), spur sidebands
appear on the VCO output spectrum at an offset frequency that
corresponds to the beat note or difference frequency between
an integer multiple of the PFD and the VCO frequency.
These spurs are named integer boundary spurs because they are
more noticeable on channels close to integer multiples of the PFD
where the difference frequency can be inside the loop band-
width. These spurs are attenuated by the loop filter.
Figure 7 shows an integer boundary spur. The RF frequency is
5800.25 MHz, and the PFD frequency is 25 MHz. The integer
boundary spur is 250 kHz from the carrier at an integer times
the PFD frequency (232 × 25 MHz = 5800 MHz). The spur also
appears on the upper sideband.
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. One such
mechanism is the feedthrough of low levels of on-chip reference
switching noise out through the RF
resulting in reference spur levels as high as –90 dBc. Care
should be taken in the PCB layout to ensure that the VCO is
well separated from the input reference to avoid a possible
feedthrough path on the board.
PFD
/MOD. The various spur mechanisms possible with
IN
PFD
pin back to the VCO,
) that allows PLL output
Rev. 0 | Page 18 of 20
LOW FREQUENCY APPLICATIONS
The specification on the RF input is 0.5 GHz minimum;
however, RF frequencies lower than this can be used providing
the minimum slew rate specification of 400 V/μs is met.
An appropriate LVDS driver can be used to square up the RF
signal before it is fed back to the ADF4157 RF input. The FIN1001
from Fairchild Semiconductor is one such LVDS driver.
FILTER DESIGN—ADIsimPLL
A filter design and analysis program is available to help the user
implement PLL design. Visit
download of the ADIsimPLL™ software. The software designs,
simulates, and analyzes the entire PLL frequency domain and
time domain response. Various passive and active filter
architectures are allowed.
INTERFACING
The ADF4157 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When latch enable (LE) is high, the 29 bits that have
been clocked into the input register on each rising edge of
SCLK are transferred to the appropriate latch. See Figure 2 for
the timing diagram and Table 6 for the latch truth table.
The maximum allowable serial clock rate is 20 MHz.
PCB DESIGN GUIDELINES FOR THE CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-20) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. The land should be centered on the pad.
This ensures that the solder joint size is maximized.
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. On the printed circuit board, there
should be a clearance of at least 0.25 mm between the thermal
pad and the inner edges of the pad pattern. This ensures that
shorting is avoided.
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated into the thermal pad at
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 ounce
of copper to plug the via. The user should connect the printed
circuit board thermal pad to AGND.
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