ADF4108BRUZ AD [Analog Devices], ADF4108BRUZ Datasheet - Page 9

• Manufacturer Part Number: ADF4108BRUZ
• Description: PLL Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
REFERENCE INPUT STAGE
The reference input stage is shown in Figure 11. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
on power-down.
RF INPUT STAGE
The RF input stage is shown in Figure 12. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A and B
counters, enables the large division ratio, N, to be realized (N =
BP + A). The dual-modulus prescaler, operating at CML levels,
takes the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. The
prescaler is programmable. It can be set in software to 8/9,
16/17, 32/33, or 64/65. It is based on a synchronous 4/5 core. A
minimum divide ratio is possible for contiguous output
frequencies. This minimum is determined by P, the prescaler
value, and is given by: (P
A AND B COUNTERS
The A and B CMOS counters combine with the dual-modulus
prescaler to allow a wide ranging division ratio in the PLL
RF
RF
IN
IN
REF
A
B
IN
GENERATOR
NC
POWER-DOWN
Figure 11. Reference Input Stage
BIAS
SW1
CONTROL
Figure 12. RF Input Stage
NO
2
NC
500Ω
– P).
SW2
SW3
100kΩ
1.6V
500Ω
BUFFER
AGND
AV
DD
TO R COUNTER
IN
pin
Rev. 0 | Page 9 of 20
feedback counter. The counters are specified to work when the
prescaler output is 300 MHz or less. Thus, with an RF input
frequency of 4.0 GHz, a prescaler value of 16/17 is valid but a
value of 8/9 is not valid.
Pulse Swallow Function
The A and B counters, in conjunction with the dual-modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is as follows:
where:
f
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler (8/9, 16/17,
and so on.).
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 6-bit swallow counter (0 to
63).
f
INPUT STAGE
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PHASE FREQUENCY DETECTOR AND CHARGE
PUMP
The phase frequency detector (PFD) takes inputs from the R
counter and N counter (N = BP + A) and produces an output
proportional to the phase and frequency difference between
them. Figure 14 is a simplified schematic. The PFD includes a
programmable delay element that controls the width of the
antibacklash pulse. This pulse ensures that there is no dead zone
in the PFD transfer function and minimizes phase noise and
reference spurs. Two bits in the reference counter latch, ABP2
and ABP1, control the width of the pulse. (See Figure 17.)
VCO
REFIN
FROM RF
is the output frequency of external voltage controlled
f
is the external reference frequency oscillator.
VCO
=
[
(
P
MODULUS
CONTROL
×
N DIVIDER
N = BP + A
B
)
PRESCALER
+
A
P/P + 1
Figure 13. A and B Counters
]
×
f
REFIN
R
LOAD
LOAD
COUNTER
COUNTER
13-BIT B
6-BIT A
ADF4108
TO PFD