ADF4108BRUZ AD [Analog Devices], ADF4108BRUZ Datasheet - Page 12

• Manufacturer Part Number: ADF4108BRUZ
• Description: PLL Frequency Synthesizer
• Manufacturer: AD [Analog Devices]

ADF4108
REFERENCE COUNTER LATCH MAP
X
= DON’T CARE
DB23
BOTH OF THESE BITS
MUST BE SET TO 0 FOR
NORMAL OPERATION.
X
RESERVED
DB22
0
DB21
0
LDP
0
1
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
LDP
TEST MODE BITS
SHOULD BE SET
TO 00 FOR NORMAL
OPERATION.
MODE BITS
OPERATION
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
T2
TEST
T1
ABP2
0
0
1
1
ABP2
BACKLASH
WIDTH
ANTI-
ABP1
ABP1
0
1
0
1
R14
2.9ns
1.3ns
6.0ns
2.9ns
ANTIBACKLASH PULSE WIDTH
Figure 17. Reference Counter Latch Map
R13
R14
0
0
0
0
.
.
.
1
1
1
1
R12
Rev. 0 | Page 12 of 20
R11
R13
0
0
0
0
.
.
.
1
1
1
1
R10
14-BIT REFERENCE COUNTER
R12
0
0
0
0
.
.
.
1
1
1
1
R9
DB9
R8
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
DB8
R7
DB7
R6
R3
0
0
0
1
.
.
.
1
1
1
1
DB6
R5
DB5
R4
R2
0
1
1
0
.
.
.
0
0
1
1
DB4
R3
DB3
R2
R1
1
0
1
0
.
.
.
0
1
0
1
DB2
R1
DIVIDE RATIO
1
2
3
4
.
.
.
16380
16381
16382
16383
C2 (0)
DB1
CONTROL
BITS
C1 (0)
DB0