CY7C199CN-12VC CYPRESS [Cypress Semiconductor], CY7C199CN-12VC Datasheet - Page 8
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CY7C199CN-12VC
Manufacturer Part Number
CY7C199CN-12VC
Description
256K (32K x 8) Static RAM
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C199CN-12VC.pdf
(14 pages)
Timing Waveforms
Write Cycle 1 (WE controlled)
Write Cycle 2 (CE controlled)
Notes
Document #: 001-06435 Rev. *B
13. This cycle is WE controlled, OE is HIGH during write.
14. Data in and/or out is high impedance if OE = V
15. During this period the IOs are in output state and input signals must not be applied.
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Data In/Out
Data In/Out
Address
Address
WE
WE
OE
CE
CE
Undefined
see footnotes
High Z
(continued)
[14, 16, 17]
[13, 14, 15]
t
HZOE
t
SA
IH
.
t
SA
t
AW
t
SCE
t
AW
Data-In Valid
t
t
WC
WC
Data-In Valid
t
t
t
SD
PWE
SD
t
SCE
t
t
HD
HA
t
HD
t
HA
CY7C199CN
High Z
Page 8 of 14
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