CY7C1518AV18 CYPRESS [Cypress Semiconductor], CY7C1518AV18 Datasheet - Page 18

• Manufacturer Part Number: CY7C1518AV18
• Description: 72-Mbit DDR-II SRAM Two-Word Burst Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Power-up Sequence in DDR-II SRAM
DDR-II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power-up Sequence
■
■
Document Number: 001-06982 Rev. *I
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐
❐
❐
Provide stable DOFF (HIGH), power and clock (K, K) for 1024
cycles to lock the DLL.
Apply V
Apply V
Drive DOFF HIGH.
V
DD
/
DOFF
V
DD
DDQ
DDQ
before V
K
K
before V
DDQ
REF
.
or at the same time as V
Unstable Clock
Clock Start (Clock Starts after
V
DD
Figure 3. Power-up Waveforms
/
V
REF
DDQ
.
V
Stable (< +/- 0.1V DC per 50ns )
DD
/
V
DLL Constraints
■
■
■
DDQ
DLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as t
The DLL functions at frequencies down to 120 MHz.
If the input clock is unstable and the DLL is enabled, then the
DLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide1024 cycles stable clock
to relock to the desired clock frequency.
Fix High (or tie to V DDQ )
> 1024 Stable clock
Stable)
CY7C1518AV18
CY7C1520AV18
Start Normal
Operation
KC Var
Page 18 of 29
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