CAT25M01 ONSEMI [ON Semiconductor], CAT25M01 Datasheet - Page 9

• Manufacturer Part Number: CAT25M01
• Description: 1 Mb SPI Serial CMOS EEPROM
• Manufacturer: ONSEMI [ON Semiconductor]

Read Operations
Read from Memory Array
followed by a 24−bit address (see Table 11 for the number
of significant address bits).
respond by shifting out data on the SO pin (as shown in
Figure 9). Sequentially stored data can be read out by simply
continuing to run the clock. The internal address pointer is
automatically incremented to the next higher address as data
is shifted out. After reaching the highest memory address,
the address counter “rolls over” to the lowest memory
address, and the read cycle can be continued indefinitely.
The read operation is terminated by taking CS high.
Read Identification Page
is achieved using the same Read command sequence as used
SCK
To read from memory, the host sends a READ instruction
After receiving the last address bit, the CAT25M01 will
Reading the additional 256−byte Identification Page (IP)
SCK
SO
CS
CS
SO
SI
SI
* Please check the Byte Address Table (Table 11).
Note: Dashed Line = mode (1, 1)
Note: Dashed Line = mode (1, 1)
0
0
0
0
0
1
0
0
2
1
0
HIGH IMPEDANCE
3
OPCODE
OPCODE
0
2
0
4
0
0
HIGH IMPEDANCE
5
3
1
6
0
4
1
7
A
Figure 10. RDSR Timing
N
8
5
1
Figure 9. READ Timing
http://onsemi.com
9
BYTE ADDRESS*
6
0
10
1
7
9
28 29 30
for Read from main memory array (Figure 9). The IPL bit
from the Status Register must be set (IPL = 1) before
attempting to read from the IP. The [A7:A0] are the address
significant bits that point to the data byte shifted out on the
SO pin. If the CS continues to be held low, the internal
address register defined by [A7:A0] bits is automatically
incremented and the next data byte from the IP is shifted out.
The byte address must not exceed the 256−byte page
boundary.
Read Status Register
command. After receiving the last bit of the command, the
CAT25M01 will shift out the contents of the status register
on the SO pin (Figure 10). The status register may be read
at any time, including during an internal write cycle.
MSB
To read the status register, the host simply sends a RDSR
8
7
9
6
31 32 33 34 35 36 37 38
A
0
10
5
MSB
7
11
6
4
DATA OUT
5
12
3
DATA OUT
4
3
13
2
2
14
1
1
0
0