CAT25M01 ONSEMI [ON Semiconductor], CAT25M01 Datasheet - Page 5

• Manufacturer Part Number: CAT25M01
• Description: 1 Mb SPI Serial CMOS EEPROM
• Manufacturer: ONSEMI [ON Semiconductor]

Status Register
number of status and control bits.
with a write operation. This bit is automatically set to 1
during an internal write cycle, and reset to 0 when the device
is ready to accept commands. For the host, this bit is read
only.
WREN/WRDI commands. When set to 1, the device is in a
Write Enable state and when set to 0, the device is in a Write
Disable state.
blocks are currently write protected. They are set by the user
with the WRSR command and are non−volatile. The user is
allowed to protect a quarter, one half or the entire memory,
by setting these bits according to Table 9. The protected
blocks then become read−only.
the WP pin. Hardware write protection is enabled when the
WP pin is low and the WPEN bit is 1. This condition
Table 8. STATUS REGISTER
Table 9. BLOCK PROTECTION BITS
Table 10. WRITE PROTECT CONDITIONS
The Status Register, as shown in Table 8, contains a
The RDY (Ready) bit indicates whether the device is busy
The WEL (Write Enable Latch) bit is set/reset by the
The BP0 and BP1 (Block Protect) bits determine which
The WPEN (Write Protect Enable) bit acts as an enable for
WPEN
WPEN
X
X
0
0
1
1
7
BP1
0
0
1
1
Status Register Bits
High
High
Low
Low
WP
IPL
X
X
6
BP0
0
1
0
1
WEL
0
1
0
1
0
1
5
0
Protected Blocks
Array Address Protected
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LIP
4
Protected
Protected
Protected
Protected
Protected
Protected
18000h−1FFFFh
10000h−1FFFFh
00000h−1FFFFh
None
5
prevents writing to the status register and to the block
protected sections of memory. While hardware write
protection is active, only the non−block protected memory
can be written. Hardware write protection is disabled when
the WP pin is high or the WPEN bit is 0. The WPEN bit, WP
pin and WEL bit combine to either permit or inhibit Write
operations, as detailed in Table 10.
whether the additional Identification Page (IPL = 1) or main
memory array (IPL = 0) can be accessed both for Read and
Write operations. The IPL bit is set by the user with the
WRSR command and is volatile. The IPL bit is
automatically reset after read/write operations.
and is non−volatile. When set to 1, the Identification Page is
permanently write protected (locked in Read−only mode).
same WRSR instruction. If the user attempts to set (“1”)
both the IPL and LIP bit in the same time, these bits cannot
be written and therefore they will remain unchanged.
The IPL (Identification Page Latch) bit determines
The LIP bit is set by the user with the WRSR command
Note: The IPL and LIP bits cannot be set to 1 using the
BP1
3
Unprotected Blocks
Protected
Protected
Protected
Writable
Writable
Writable
BP0
2
Quarter Array Protection
Half Array Protection
Full Array Protection
No Protection
WEL
Protection
1
Status Register
Protected
Protected
Protected
Protected
Writable
Writable
RDY
0