SI5338 SILABS [Silicon Laboratories], SI5338 Datasheet - Page 8

• Manufacturer Part Number: SI5338
• Description: I2C-PROGRAMMABLE ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR
• Manufacturer: SILABS [Silicon Laboratories]

Si5338
Table 6. Input and Output Clock Characteristics (Continued)
(V
8
Parameter
Input Impedance
Input Capacitance
Input Clock (DC-Coupled Single-Ended Input Clock on Pins IN3/4)
Frequency
Input Voltage
Input Voltage Swing
Rise/Fall Time
Duty Cycle
Input Capacitance
Output Clocks (Differential)
Frequency
LVPECL Output Voltage
LVDS Output Voltage
(2.5/3.3 V)
LVDS Output Voltage
(1.8 V)
HCSL Output Voltage
Rise/Fall Time
Duty Cycle
Notes:
DD
1. For best jitter performance, keep the input slew rate on pins 1,2,5,6 faster than 0.3 V/ns
2. Not in PLL bypass mode.
3. For best jitter performance, keep the input single ended slew rate on pins 3 or 4 faster than 1 V/ns
4. Only two unique frequencies above 350 MHz can be simultaneously output, Fvco/4 and Fvco/6.
5. Includes effect of internal series 22  resistor.
= 1.8 V –5% to +10%, 2.5 V ±10%, or 3.3 V ±10%, T
4
2,3
2
Symbol
V
V
V
V
t
f
V
V
V
V
t
R
C
DC
C
SEPP
SEPP
SEPP
SEPP
DC
R
OUT
R
f
V
IN
OC
OC
OC
OC
/t
/t
IN
IN
IN
I
F
F
peak-to-peak single-
peak-to-peak single-
peak-to-peak single-
peak-to-peak single-
Test Condition
LVPECL, LVDS
common mode
common mode
common mode
common mode
ended swing
ended swing
ended swing
ended swing
20%–80%
20%–80%
< 4 ns tr/tf
200 MHz
CMOS
HCSL
A
Rev. 0.6
= –40 to 85 °C)
1.125
0.575
–0.1
0.16
0.16
0.55
0.25
0.25
0.35
Min
367
550
0.8
0.8
10
40
45
—
—
—
—
—
5
V
DDO
0.875
0.375
0.725
0.35
0.35
Typ
3.5
2.0
0.8
1.2
—
—
—
—
—
—
—
—
—
—
–1.45 V
—
—
VDD+10%
473.33
1.275
0.400
3.63
0.96
0.45
0.95
0.45
0.85
Max
200
350
710
250
450
60
55
—
—
—
—
2
Units
MHz
MHz
MHz
MHz
MHz
Vpp
V
V
V
V
k
pF
pF
ns
ps
%
%
V
V
V
V
V
PP
PP
PP
PP