AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 60

• Manufacturer Part Number: AD9518-4A-PCBZ
• Description: 6-Output Clock Generator with Integrated 1.6 GHz VCO
• Manufacturer: AD [Analog Devices]

AD9518-4
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs (because they are open emitter) require a
dc termination to bias the output transistors. The simplified
equivalent circuit in Figure 43 shows the LVPECL output stage.
In most applications, an LVPECL far-end Thevenin termination
(see Figure 53) or Y-termination (see Figure 54) is recommended.
In each case, the V
V
Figure 55). In the case of Figure 55, pull-down resistors of <150 Ω
are not recommended when V
the LVPECL drivers may result. The minimum recommended
pull-down resistor size for V
The resistor network is designed to match the transmission line
impedance (50 Ω) and the switching threshold (V
S_LVPECL
Figure 53. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
V
V
S_LVPECL
S_LVPECL
voltage. If it does not, ac coupling is recommended (see
LVPECL
LVPECL
Figure 54. DC-Coupled 3.3 V LVPECL Y-Termination
S
(NOT COUPLED)
of the receiving buffer should match the
SINGLE-ENDED
Z
Z
0
0
50Ω
50Ω
= 50Ω
= 50Ω
S_LVPECL
S_LVPECL
127Ω
83Ω
= 2.5 V is 100 Ω.
= 3.3 V; if used, damage to
V
50Ω
S_DRV
50Ω
50Ω
127Ω
83Ω
V
S
LVPECL
LVPECL
= 3.3V
V
S
S
− 1.3 V).
Rev. B | Page 60 of 64
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 54, where V
resistor that is connected to ground should be changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to provide
50 Ω termination to a dc voltage that is below V
driver. In this case, V
the receiving buffer. Although the resistor combination shown
in Figure 54 results in a dc bias point of V
actual common-mode voltage is V
is additional current flowing from the
through the pull-down resistor.
The circuit is identical when V
down resistor is 62.5 Ω and the pull-up resistor is 250 Ω.
V
S_LVPECL
Figure 55. AC-Coupled LVPECL with Parallel Transmission Line
LVPECL
200Ω
0.1nF
0.1nF
200Ω
S_LVPECL
TRANSMISSION LINE
100Ω DIFFERENTIAL
on the
(COUPLED)
S_LVPECL
S_LVPECL
S_LVPECL
AD9518
= 2.5 V, the 50 Ω termination
= 2.5 V, except that the pull-
AD9518
− 1.3 V because there
S_LVPECL
100Ω
should equal V
Data Sheet
OL
LVPECL driver
− 2 V, the
of the LVPECL
LVPECL
V
S
S
of