AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 33

• Manufacturer Part Number: AD9518-4A-PCBZ
• Description: 6-Output Clock Generator with Integrated 1.6 GHz VCO
• Manufacturer: AD [Analog Devices]

Data Sheet
VCO Calibration
The
operation over process and temperature. VCO calibration centers
the dc voltage at the internal VCO input (at the LF pin) for the
selected configuration; this is normally required only during
initial configuration and any time the PLL settings change. VCO
calibration is controlled by a calibration controller driven by the
R divider output. The calibration requires that the input reference
clock be present at the REFIN pins, and that the PLL be set up
properly to lock the PLL loop. During the first initialization after
a power-up or a reset of the AD9518, a VCO calibration sequence
is initiated by setting Register 0x018[0] = 1b. This can be done
during initial setup, before executing an update registers operation
(Register 0x232[0] = 1b). Subsequent to initial setup, a VCO
calibration sequence is initiated by resetting Register 0x018[0] = 0b,
executing an update registers operation, setting Register 0x018[0] =
1b, and executing another update registers operation. A readback
bit (Bit 6 in Register 0x1F) indicates when a VCO calibration is
finished by returning a logic true (that is, 1b).
The sequence of operations for the VCO calibration is as follows:
1.
2.
3.
4.
5.
REFIN (REF1)
REFIN (REF2)
AD9518
Program the PLL registers to the proper values for the PLL
loop. Note that that automatic holdover mode must be
disabled, and the VCO divider must not be set to “Static. ”
Ensure that the input reference signal is present.
For the initial setting of the registers after a power-up or reset,
initiate VCO calibration by setting Register 0x018[0] = 1b.
Subsequently, whenever a calibration is desired, set
Register 0x018[0] = 0b, update registers; and then set
Register 0x018[0] = 1b, update registers.
A sync operation is initiated internally, causing the outputs
to go to a static state determined by normal sync function
operation.
The VCO calibrates to the desired setting for the requested
VCO frequency.
BYPASS
CLK
CLK
LF
on-chip VCO must be calibrated to ensure proper
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
SWITCHOVER
STATUS
REFERENCE
REF_SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
N DIVIDER
DIVIDER
Figure 39. Reference and VCO Status Monitors
R
COUNTERS
DISTRIBUTION
REFERENCE
A/B
RSET
Rev. B | Page 33 of 64
0
1
VCO STATUS
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
6.
7.
8.
A SYNC is executed during the VCO calibration; therefore, the
outputs of the
which prevents unwanted frequencies from being produced.
However, at the end of a VCO calibration, the outputs may
resume clocking before the PLL loop is completely settled.
The VCO calibration clock divider is set as shown in Table 44
(Register 0x018[2:1]).
The calibration divider divides the PFD frequency (reference
frequency divided by R) down to the calibration clock. The
calibration occurs at the PFD frequency divided by the
calibration divider setting. Lower VCO calibration clock
frequencies result in longer times for a calibration to be
completed.
The VCO calibration clock frequency is given by
where:
f
R is the value of the R divider.
cal_div is the division set for the VCO calibration divider
(Register 0x018[2:1]).
The VCO calibration takes 4400 calibration clock cycles.
Therefore, the VCO calibration time in PLL reference clock
cycles is given by
REFIN
Internally, the SYNC signal is released, allowing outputs
to continue clocking.
The PLL loop is closed.
The PLL locks.
f
Time to Calibrate VCO =
4400 × R × cal_div PLL Reference Clock Cycles
is the frequency of the REFIN signal.
CAL_CLOCK
= f
AD9518
FREQUENCY
DETECTOR
REFIN
DETECT
PHASE
LOCK
/(R × cal_div)
are held static during the calibration,
CPRSET VCP
CHARGE
PUMP
HOLD
AD9518-4
LD
CP
STATUS