AD9518-4A-PCBZ AD [Analog Devices], AD9518-4A-PCBZ Datasheet - Page 50

• Manufacturer Part Number: AD9518-4A-PCBZ
• Description: 6-Output Clock Generator with Integrated 1.6 GHz VCO
• Manufacturer: AD [Analog Devices]

AD9518-4
Reg.
Addr.
(Hex)
0x018
0x019
Bits
[1:0]
[6:5]
4
3
[2:1]
0
[7:6]
[5:3]
[2:0]
Name
Antibacklash
pulse width
Lock detect
counter
Digital lock detect
window
Disable digital
lock detect
VCO cal divider
VCO cal now
R, A, B counters,
SYNC pin reset
R path delay
N path delay
Description
1
0
0
1
1
Required consecutive number of PFD cycles with edges inside lock detect window before the DLD indicates a locked
condition.
6
0
0
1
1
If the time difference of the rising edges at the inputs to the PFD is less than the lock detect window time, the digital lock
detect flag is set. The flag remains set until the time difference is greater than the loss-of-lock threshold.
0: high range (default).
1: low range.
Digital lock detect operation.
0: normal lock detect operation (default).
1: disables lock detect.
VCO calibration divider. Divider used to generate the VCO calibration clock from the PLL reference clock.
2
0
0
1
1
Bit used to initiate VCO calibration. This bit must be toggled from 0b to 1b in the active registers. To initiate calibration,
use the following three steps: first, ensure that the input reference signal is present; second, set to 0b (if not zero
already), followed by the update all registers bit (Register 0x232, Bit 0); and third, program to 1b, again followed by the
update all registers bit (Register 0x232, Bit 0). Clearing this bit discards the VCO calibration and usually results in the
PLL losing lock. The user must ensure that the holdover enable bits in Register 0x01D = 00b during VCO calibration.
7
0
0
1
1
R path delay (default = 0x00); see Table 2.
N path delay (default = 0x00); see Table 2.
0
0
1
0
1
5
0
1
0
1
1
0
1
0
1
6
0
1
0
1
Antibacklash Pulse Width (ns)
2.9 (default); this is the recommended setting, and it does not normally need to be changed
1.3; this setting may be necessary if the PFD frequency > 50 MHz
6.0.
2.9.
PFD Cycles to Determine Lock
5 (default).
16.
64.
255.
VCO Calibration Clock Divider
2. This setting is fine for PFD frequencies < 12.5 MHz. The PFD frequency is f
4. This setting is fine for PFD frequencies < 25 MHz.
8. This setting is fine for PFD frequencies < 50 MHz.
16 (default). This setting is fine for any PFD frequency but also results in the longest VCO calibration time.
Action
Does nothing on SYNC (default).
Asynchronous reset.
Synchronous reset.
Does nothing on SYNC .
Rev. B | Page 50 of 64
REF
/R.
Data Sheet