LMX2542LQ2121 NSC [National Semiconductor], LMX2542LQ2121 Datasheet - Page 20

• Manufacturer Part Number: LMX2542LQ2121
• Description: PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO
• Manufacturer: NSC [National Semiconductor]

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Reg
Reg
R3
R4
2.0 Programming Description
2.4.5 VCO_CUR[1:0] - RF VCO Dynamic Current (R2[9:8])
The VCO_CUR control word is used to set the dynamic current for the RF VCO. A maximum dynamic current is recommended,
and is achieved when VCO_CUR[1:0] word = 11.
2.5 R3 REGISTER
The R3 register is used for internal testing of the device and is not intended for customer use. The register address bits are
R3[2:0] = 011. Register R3 is active only when the SPI_DEF bit in Register R0 is set to 0.
2.6 R4 REGISTER
The R4 register contains the IF_B and IF_A control words. The register address bits are R4[3:0] = 0111. Register R4 is active only
when the SPI_DEF bit in Register R0 is set to 0. Regsiter R4 should only be used to set the IF N counter if the default value is
not desired. The detailed descriptions and programming information for each control word is discussed in the following sections.
2.6.1 IF_B[8:0] - IF Synthesizer Programmable Binary Counter (B Counter) (R4[12:4])
The IF_B control word is used to setup the IF synthesizer’s B counter. The B counter is a 9-bit programmable binary counter used
in the programmable feedback divider. The IF_B control word can be programmed to values ranging from 1 to 511. Divide ratios
less than 1 are prohibited.
2.6.2 IF_A[3:0] - IF Synthesizer Swallow Counter (A Counter) (R4[16:13])
The IF_A control word is used to setup the IF synthesizer’s A counter. The A counter is a 4-bit swallow counter used in the
programmable feedback divider. The IF_A control word can be programmed to values ranging from 0 to 15.
MSB
MSB
23
23
0
0
Divide Ratio
22
22
0
0
15
0
1
•
21
21
0
0
0
1
•
•
20
20
0
0
19
19
0
0
Divide Ratio
VCO_CUR[1:0]
18
18
511
0
0
1
2
•
17
17
0
0
3
0
0
1
•
16
16
0
15
15
0
IF_A
[3:0]
8
0
0
1
•
DATA[20:0] FIELD
DATA[19:0]
SHIFT REGISTER BIT LOCATION
SHIFT REGISTER BIT LOCATION
14
14
(Continued)
0
1
0
•
•
7
0
0
1
•
13
13
0
2
0
0
1
12
12
•
20
1
6
0
0
1
•
11
11
0
5
0
0
1
•
IF_A[3:0]
10
10
IF_B[8:0]
1
4
0
0
1
•
9
0
9
IF_B
[8:0]
3
0
0
1
8
0
8
•
RF VCO Current Magnitude
1
0
0
1
•
7
1
7
2
0
0
1
•
Maximum
Minimum
6
0
6
1
0
1
1
•
•
•
5
0
5
0
1
0
1
•
4
1
4
3
0
3
0
0
0
1
1
•
ADDRESS
2
0
2
1
FIELD
ADDRESS
[3:0]
FIELD
[2:0]
1
1
1
1
LSB
LSB
0
1
0
1