LMX2542LQ2121 NSC [National Semiconductor], LMX2542LQ2121 Datasheet - Page 15

• Manufacturer Part Number: LMX2542LQ2121
• Description: PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO
• Manufacturer: NSC [National Semiconductor]

Reg
R0 SPI_
R1
R2
R3
R4
R5
R6
2.0 Programming Description
2.1 MICROWIRE INTERFACE
The MICROWIRE Serial Port Interface (SPI) has a 24-bit shift register to store the incoming DATA bits temporarily. The incoming
DATA is loaded into the shift register from MSB to LSB. The data is shifted at the rising edge of the CLK signal. When the LE
signal transitions from LOW to HIGH, the DATA stored in the shift register is transferred to the proper register depending on the
state of the ADDRESS bits. The selection of the particular register is determined by the address bits equal to the binary
representation of the number of the control register.
At start-up, the 24-bit shift register is loaded via the MICROWIRE interface. The loading requires 3 default words, with register
R2 loaded first, and R0 loaded last. Once loaded, the RF VCO frequency can then be changed by only programming register R0
appropriately. If an IF frequency other than the default value is desired, the SPI_DEF bit should be set to 0, and registers R4 and
R5 programmed appropriately.
2.1.1 Control Register Content Map
The control register content map describes how the bits within each control register are allocated to specific control functions. The
bits that are marked 0 should be programmed as such to ensure proper device operation.
Note: Numbers in Bold represent the ADDRESS bits.
MSB
DEF
23
0
1
0
0
0
0
22
1
1
1
0
0
0
0
RF_
LD
21
1
0
0
0
0
0
20
0
0
0
0
0
0
0
19
1
1
0
0
0
0
18
0
0
0
0
0
0
RF_B
[3:0]
17
0
0
0
0
0
0
16
0
1
0
0
1
15
1
0
0
0
1
IF_A
[3:0]
RF_A
[2:0]
SHIFT REGISTER BIT LOCATION
14
0
0
0
0
1
13
1
0
0
1
12
15
0
0
1
1
11
1
0
0
1
10
0
0
1
1
VCO_CUR
IF_R
[8:0]
9
1
0
1
[1:0]
IF_B
[8:0]
8
0
0
1
RF_FN
[10:0]
FREQ
OSC_
7
0
1
1
IF_FREQ
6
1
0
1
[1:0]
OB_CRL
5
0
0
[1:0]
IF_CUR
4
1
0
1
[1:0]
RF_
EN
3
0
0
1
1
FREQ_
OFF
IF_
EN
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2
0
1
1
1
1
0
0
1
1
1
1
1
LSB
0
0
1
0
1
1
1
1