VSC8163QR VITESSE [Vitesse Semiconductor Corporation], VSC8163QR Datasheet - Page 5

• Manufacturer Part Number: VSC8163QR
• Description: OC-48 16:1 SONET/SDH MUX with Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

G52216-0, Rev 3.3
01/05/01
Preliminary Data Sheet
VSC8163
Clock Generator
The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip
loop filter. The loop bandwidth of the PLL is within the SONET specified limit of 2MHz.
ence, 155.52MHz. REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0”
designates REFCLK input as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 2ps of RMS jitter to the output. The
VSC8163 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8163 itself during such
conditions.
Low-Speed Inputs
CLK. Off-chip termination of these inputs is required. For AC-coupling, a bias voltage suitable for AC-cou-
pling needs to be provided (see Figure 7 for external biasing resistor scheme).
where this does not hold, direct DC connection is possible. All serial data inputs have the same circuit topology,
as shown in Figure 7. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the
An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input.
The REFCLK should be of high quality since noise on the REFCLK below the loop band width of the PLL
The incoming low-speed data and reference clock input are received by LVPECL inputs D[15:0] and REF-
In most situations these inputs will have high transition density and little DC offset. However, in cases
The customer can select to provide either a 77.76MHz reference (recommended), or the 2x of that refer-
Z
O
Z
O
Figure 7: AC Termination of Low-Speed LVPECL REFCLK, D[15:0] Inputs
V
V
V
V
C
CC
EE
C
CC
EE
IN
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
IN
R1
R2
R1
R2
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
SEMICONDUCTOR CORPORATION
Chip Boundary
Internet: www.vitesse.com
V
V
CC
EE
= 3.3V
= 0V
Split-end equivalent termination is Z
R1 = 83
MUX with Clock Generator
R2 = 125 , Z
OC-48 16:1 SONET/SDH
V
C
for AC operation
CC
R1||R2 = Z
IN
R2 + V
R1+R2
typ = 100nF
0
=50 , V
EE
o
R1
TERM
= V
0
to V
BIAS
= V
TERM
CC
-2V
Page 5