VSC8163QR VITESSE [Vitesse Semiconductor Corporation], VSC8163QR Datasheet - Page 2

• Manufacturer Part Number: VSC8163QR
• Description: OC-48 16:1 SONET/SDH MUX with Clock Generator
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

Page 2
OC-48 16:1 SONET/SDH
MUX with Clock Generator
Functional Description
Low-Speed Interface
The Upstream Device should then generate a CLK16I phase aligned with the data. The VSC8163 will latch
D[15:0] ± on the rising edge of CLK16I+. The data must meet setup and hold times with respect to CLK16I (see
Table 2). In addition to the CLK16O clock output, there also exists a utility REFCLKO output signal, which is a
clock with the same rate as that presented at the REFCLK input.
locked to the reference clock, RESET must be held low for a minimum of five CLK16 cycles ( > 32ns) to ini-
tialize the FIFO, then RESET should be set high and held constant for continuous FIFO operation. For the
transparent mode of operation (no FIFO), simply hold RESET at a constant low state (see Figure 2).
and CLK16I. Once RESET is asserted and the FIFO initialized, the delay between CLK16O and CLK16I can
decrease or increase up to one period of the low-speed clock (6.4ns). Should this delay drift exceed one period,
the write pointer and the read pointer could point to the same word in the FIFO, resulting in a loss of transmitted
data (a FIFO overflow). In the event of a FIFO overflow, an active low FIFO_WARN signal is asserted (for a
minimum of 5 CLK16I cycles) which can be used to initiate a reset signal from an external controller.
transmission line can be DC terminated with a split-end termination scheme (see Figure 3), or DC terminated by
50
substituted for the traditional 50 to V
ods. Figure 5 illustrates an example AC-coupling method for the occasion when the downstream device pro-
vides the bias point for AC-coupling. If the downstream device were to have internal termination, the line-to-
line 100 resistor may not be necessary.
The Upstream Device should use the CLK16O as the timing source for its final output latch (see Figure 1).
A FIFO exists within the VSC8163 to eliminate difficult system loop timing issues. Once the PLL has
The use of a FIFO permits the system designer to tolerate an arbitrary amount of delay between CLK16O
The CLK16O ± output driver is a LVPECL output driver designed to drive a 50
to V
CC
-2V on each line (see Figure 4). At any time, the equivalent split-end termination technique can be
Upstream
Device
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
Figure 1: Low-Speed Systems Interface
VITESSE
SEMICONDUCTOR CORPORATION
CC
REFCLK
-2V on each line. AC-coupling can be achieved by a number of meth-
CLK16O
CLK16I
x16
Internet: www.vitesse.com
2.488GHz
PLL
Write
Read
Divide by 16
16 x 5 FIFO
Preliminary Data Sheet
VSC8163
transmission line. The
VSC8163
G52216-0, Rev 3.3
01/05/00