VSC8116QP VITESSE [Vitesse Semiconductor Corporation], VSC8116QP Datasheet - Page 5

• Manufacturer Part Number: VSC8116QP
• Description: ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8116
G52220-0, Rev 4.1
1/8/00
Data Sheet
Split Loopback
facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized
and presented to RXOUT[0:7], and TXIN[0:7] will not be serialized and present to TXDATAOUT.
Loop Timing
is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single
external source.
TXDATAOUT
RXDATAIN
FACLOOP
TXDATAOUT
RXCLKIN
Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and
LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU
EQULOOP
RXDATAIN
RXCLKIN
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
Q D
D Q
D
Q
Q D
Figure 4: Equipment Loopback Data Path
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
1
0
1
0
Figure 5: Split Loopback Datapath
0
1
0
1
0
1
0
1
PLL
Serial to
Parallel
Parallel to
Serial
1:8
8:1
Serial to
Parallel
Parallel to
Serial
PLL
1:8
8:1
8
Mux/Demux with Integrated Clock Generation
ATM/SONET/SDH 622/155Mb/s Transceiver
8
8
Q D
Q D
D
D
Q
Q
EQULOOP
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
RXOUT[7:0]
RXLSCKOUT
TXIN[7:0]
TXLSCKOUT
Page 5