VSC8116QP VITESSE [Vitesse Semiconductor Corporation], VSC8116QP Datasheet - Page 19

• Manufacturer Part Number: VSC8116QP
• Description: ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation
• Manufacturer: VITESSE [Vitesse Semiconductor Corporation]

VSC8116
G52220-0, Rev 4.1
1/8/00
Data Sheet
Table 14: AC Coupling Component Values
TTL Input Structure
erances (see Table 11). The input structure, shown in Figure 12, uses a current limiter to avoid overdriving the
input FETs.
Layout of the High Speed Signals
include using controlled impedance lines (50 ohms) and keeping the distance between components to an abso-
lute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will
help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition
the output pull down resistor R2 should be placed as close to the VSC8116 pin as possible while the AC-cou-
pling capacitor C2 and the biasing resistors R3, R4 should be placed as close as possible to the optics input pin.
The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps
in reducing discontinuities.
Ground Planes
tioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to inter-
fere with the ground return currents on the signal lines. In addition, the smaller the ground planes the less
effective they are in reducing ground bounce noise and the more difficult to decouple. Sectioning of the positive
supplies can provide some isolation benefits.
Analog Power Supplies
planes. The dedicated PLL power (VDDA) and ground (VSSA) pins need to have quiet supply planes to mini-
mize jitter generation within the clock synthesis unit. This is accomplished by either using a ferrit bead or a C-
L-C choke ( filter).
The TTL inputs of the VSC8116 are 3.3V TTL which can accept 5.0V TTL levels within a given set of tol-
The routing of the High Speed signals should be done using good high speed design practices. This would
The ground plane for the components used in the High Speed interface should be continuous and not sec-
Good analog design practices should be applied to the board design for the analog ground and power
C1, C2, C3, C4
Component
R1
R2
R3
R4
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: [phone]
VITESSE
VITESSE SEMICONDUCTOR CORPORATION
SEMICONDUCTOR CORPORATION
.01uf High Frequency
Mux/Demux with Integrated Clock Generation
ATM/SONET/SDH 622/155Mb/s Transceiver
270 ohms
190 ohms
75 ohms
68 ohms
Value
Tolerance
10%
5%
5%
1%
1%
Page 19