APA075-BGB ACTEL [Actel Corporation], APA075-BGB Datasheet - Page 38
APA075-BGB
Manufacturer Part Number
APA075-BGB
Description
ProASIC Flash Family FPGAs
Manufacturer
ACTEL [Actel Corporation]
Datasheet
1.APA075-BGB.pdf
(174 pages)
- Current page: 38 of 174
- Download datasheet (5Mb)
The following is an APA750 example using a shift register design with 13,440 storage tiles (Register) and 0 logic tiles.
This design has one clock at 10 MHz, and 24 outputs toggling at 5 MHz. We then calculate the various components as
follows:
P
P
P
P
=> P
P
=> P
P
=> P
P
=> 361 mW
P
P
1 -3 2
=> P
=> P
=> P
dc
clock
storage
logic
outputs
inputs
memory
ac
total
ProASIC
+ P
ms
mc
C
V
Fp
N
Fs
R
q
Fq
p
outputs
inputs
memory
load
DDP
memory
clock
storage
logic
ac
= 374 mW (typical)
= 10 MHz
= 13,440
PLUS
= 0 (no logic tiles in this shift register)
= 0 mW
= (P1 + (P2*R) - (P7*R
= 13,440 (in a shift register 100% of storage tiles are toggling at each clock cycle and Fs = 10 MHz)
= P8 * q * Fq = 0.3 mW
=
=
=
=
= (P4 + (C
= 0 mW
= P5 * ms * Fs = 147.8 mW
=
=
Flash Family FPGAs
40 pF
3.3 V
24
5 MHz
=
1
10 MHz
0 (no RAM/FIFO blocks in this shift register)
load
* V
DDP
2
2
)) * Fs = 121.5 mW
)) * p * Fp = 91.4 mW
v5.7
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