CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 26

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
Switching Waveforms
Read Cycle Timing
Note:
22. On this diagram, when CE is LOW: CE
Data Out (Q)
GW, BWE,
ADDRESS
ADSP
ADSC
BWx
ADV
CLK
OE
CE
t
ADS
t AS
t CES
[22]
A1
t
ADH
t AH
t CEH
t
CH
High-Z
t CYC
t WES
t
CL
Single READ
t CLZ
t WEH
t CO
1
is LOW, CE
t ADS
A2
Q(A1)
t ADH
t OEHZ
2
t ADVS
is HIGH and CE
t ADVH
t OELZ
t OEV
Q(A2)
DON’T CARE
t DOH
3
t CO
is LOW. When CE is HIGH: CE
Q(A2 + 1)
ADV
suspends
burst.
UNDEFINED
Q(A2 + 2)
BURST READ
1
is HIGH or CE
Q(A2 + 3)
2
is LOW or CE
A3
Q(A2)
Burst continued with
new base address
Burst wraps around
to its initial state
CY7C1360B
CY7C1362B
3
Q(A2 + 1)
is HIGH.
t CHZ
Deselect
cycle
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