CY7C1360B CYPRESS [Cypress Semiconductor], CY7C1360B Datasheet - Page 20

• Manufacturer Part Number: CY7C1360B
• Description: 9-Mbit (256K x 36/512K x 18) Pipelined SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05291 Rev. *C
Identification Register Definitions
Identification Codes
Scan Register Sizes
Revision Number (31:29)
Device Depth (28:24)
Device Width (23:18)
Cypress Device ID (17:12)
Cypress JEDEC ID Code (11:1)
ID Register Presence Indicator (0)
Instruction
Bypass
ID
Boundary Scan Order
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Instruction
Instruction Field
Register Name
Code
000
001
010
011
100
101
110
111
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1 compliant.
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.
Forces all SRAM output drivers to a High-Z state.
Do Not Use: This instruction is reserved for future use.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1 compliant.
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Do Not Use: This instruction is reserved for future use.
Do Not Use: This instruction is reserved for future use.
00000110100
CY7C1360B
(256KX36)
000000
100110
01010
001
1
Bit Size(x36)
00000110100
CY7C1362B
(512KX18)
000000
010110
32
71
01010
3
1
001
1
Description
Describes the version number
Reserved for Internal Use
Defines memory type and architecture
Defines width and density
Allows unique identification of SRAM vendor
Indicates the presence of an ID register
Description
Bit Size(x18)
32
71
3
1
CY7C1360B
CY7C1362B
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