CY7C1355C-100BZC CYPRESS [Cypress Semiconductor], CY7C1355C-100BZC Datasheet - Page 5

• Manufacturer Part Number: CY7C1355C-100BZC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05688 Rev. *D
Pin Definitions
Functional Overview
The CY7C1379C is a synchronous flow-through burst SRAM
designed specifically to eliminate wait states during
Write-Read transitions. All synchronous inputs pass through
input registers controlled by the rising edge of the clock. The
clock signal is qualified with the Clock Enable input signal
(CEN). If CEN is HIGH, the clock signal is not recognized and
all internal states are maintained. All synchronous operations
are qualified with CEN. Maximum access delay from the clock
rise (t
Accesses can be initiated by asserting all three Chip Enables
(CE
Enable (CEN) is active LOW and ADV/LD is asserted LOW,
the address presented to the device will be latched. The
access can either be a read or write operation, depending on
the status of the Write Enable (WE). BW
conduct byte write operations.
Write operations are qualified by the Write Enable (WE). All
writes are simplified with on-chip synchronous self-timed write
circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) simplify depth expansion.
All operations (Reads, Writes, and Deselects) are pipelined.
ADV/LD should be driven LOW once the device has been
deselected in order to load a new address for the next
operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
V
NC
V
SS
SS
Name
1
/DNU
, CE
CDV
3
2
are ALL asserted active, (3) the Write Enable input
) is 6.5 ns (133-MHz device).
, CE
42,43,51,66,80,8
3
1,16,30,38,39,
) active at the rising edge of the clock. If Clock
26,40,55,60,
67,71,76,90,
5,10,17,21,
4,95,96
TQFP
(continued)
14
J6,J7,K5,K6,K
7,L5,L6,L7,M5
C2,C10,C11,H
N10,N11,P1,P
H10,N1,N2,
B9,B11,C1,
P11,R2,R5,
A1,A11,B1,
G6,G7,H5,
C4,C5,C6,
C7,C8,D5,
D6,D7,E5,
F6,F7,G5,
E6,E7,F5,
H6,H7,J5,
N5,N6,N7
1,H3,H9,
2,P5,P7,
,M6,M7,
FBGA
N4,N8
R7
-
1
, CE
[A:D]
2
can be used to
, CE
Ground/DNU This pin can be connected to Ground or should be left floating.
3
Ground
) and an
I/O
1
–
, CE
2
,
Ground for the device.
No Connects. Not Internally connected to the die.
18M, 36M, 72M, 144M, 288M, 576M, and 1G are address
expansion pins and are not internally connected to the die.
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output will be tri-stated
immediately.
Burst Read Accesses
The CY7C1379C has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW in order to load a new address into the
SRAM, as described in the Single Read Access section above.
The sequence of the burst counter is determined by the MODE
input signal. A LOW input on MODE selects a linear burst
mode, a HIGH selects an interleaved burst sequence. Both
burst counters use A0 and A1 in the burst sequence, and will
wrap around when incremented sufficiently. A HIGH input on
ADV/LD will increment the internal burst counter regardless of
the state of chip enable inputs or WE. WE is latched at the
beginning of a burst cycle. Therefore, the type of access (Read
or Write) is maintained throughout the burst sequence.
Single Write Accesses
Write access are initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
and CE
is asserted LOW. The address presented to the address bus
is loaded into the Address Register. The write signals are
latched into the Control Logic block. The data lines are
automatically tri-stated regardless of the state of the OE input
signal. This allows the external logic to present the data on
DQs.
3
are ALL asserted active, and (3) the Write signal WE
Description
CY7C1379C
Page 5 of 15
1
, CE
2
,