CY7C1355C-100BZC CYPRESS [Cypress Semiconductor], CY7C1355C-100BZC Datasheet - Page 3

• Manufacturer Part Number: CY7C1355C-100BZC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05688 Rev. *D
Pin Configurations
Pin Definitions
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
0
, A
Name
1
2
3
A
B
C
D
G
H
K
M
N
R
E
F
L
P
A
C
J
, BW
, BW
1
, A
NC/576M
NC/144M
B
D
NC/1G
,
MODE
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
NC
37,36,32,33,34,3
47,48,49,50,81,8
1
C
C
C
C
D
D
D
D
2,83,99,100
93,94,95,96
5,44,45,46,
TQFP
88
85
89
98
97
92
NC/72M
NC/36M
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
NC
NC
2
A
A
DD
(continued)
C
C
C
C
D
D
D
D
R9,R10,R11
V
V
V
V
V
V
V
V
V
V
B10,P3,P4,
P8,P9,P10,
CE2
A9,A10,B2
CE
R3,R4,R8,
R6,P6,A2,
B5,A5,A4,
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
3
A
A
FBGA
1
B4
B7
A8
B6
A3
B3
A6
BW
BW
V
V
V
V
V
V
V
V
V
V
V
A
A
4
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
SS
C
D
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
165-Ball FBGA Pinout
Input-Clock
CY7C1379C (256K x 32)
Input-
Input-
Input-
Input-
Input-
Input-
Input-
I/O
BW
BW
V
V
V
V
V
V
V
V
V
V
NC
NC
NC
5
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
B
A
Address Inputs used to select one of the 256K address
locations. Sampled at the rising edge of the CLK. A
to the two-bit burst counter.
Byte Write Inputs, active LOW. Qualified with WE to conduct
writes to the SRAM. Sampled on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge
of CLK if CEN is active LOW. This signal must be asserted LOW
to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address
counter or load a new address. When HIGH (and CEN is
asserted LOW) the internal burst counter is advanced. When
LOW, a new address can be loaded into the device for an access.
After being deselected, ADV/LD should be driven LOW in order
to load a new address.
Clock Input. Used to capture all synchronous inputs to the
device. CLK is qualified with CEN. CLK is only recognized if CEN
is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.
Chip Enable 3 Input, active LOW. Sampled on the rising edge
of CLK. Used in conjunction with CE
the device.
CLK
CE
V
V
V
V
V
V
V
V
V
NC
V
A1
A0
6
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
3
CEN
WE
V
V
V
V
V
V
V
V
V
V
NC
NC
NC
7
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
ADV/LD
V
V
V
V
V
V
V
V
V
V
V
OE
A
A
8
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
Description
NC/18M
V
V
V
V
V
V
V
V
V
V
2
NC
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1
1
A
A
A
9
, and CE
and CE
and CE
CY7C1379C
3
2
3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NC
NC
NC
to select/deselect
to select/deselect
to select/deselect
10
A
A
A
A
B
B
B
B
A
A
A
A
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NC/288M
NC
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
are fed
NC
NC
NC
11
ZZ
A
B
B
B
B
A
A
A
A