CY7C1355C-100AXI CYPRESS [Cypress Semiconductor], CY7C1355C-100AXI Datasheet - Page 13

• Manufacturer Part Number: CY7C1355C-100AXI
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05539 Rev. *E
TAP Timing
TAP AC Switching Characteristics
Clock
t
t
t
t
Output Times
t
t
Set-up Times
t
t
t
Hold Times
t
t
t
Notes:
10. t
11. Test conditions are specified using the load in TAP AC Test Conditions. t
Parameter
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
CS
and t
CH
refer to the set-up and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH Time
TCK Clock LOW Time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Set-Up to TCK Clock Rise
TDI Set-Up to TCK Clock Rise
Capture Set-Up to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
Test Mode Select
Test Data-Out
Test Data-In
Test Clock
(TDO)
(TMS)
(TCK)
(TDI)
1
Description
Over the Operating Range
t TMSS
t TDIS
2
t TMSH
t TDIH
t TH
DON’T CARE
R
/t
t
F
TL
= 1 ns.
3
t CYC
[10, 11]
UNDEFINED
4
t TDOX
t TDOV
5
Min.
50
20
20
0
5
5
5
5
5
5
6
Max.
20
10
CY7C1355C
CY7C1357C
Page 13 of 28
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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