CY7C1215F-133AC CYPRESS [Cypress Semiconductor], CY7C1215F-133AC Datasheet - Page 4

• Manufacturer Part Number: CY7C1215F-133AC
• Description: 1-Mb (32K x 32) Pipelined Sync SRAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-05421 Rev. **
Pin Definitions
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
The CY7C1215F supports secondary cache in systems
utilizing either a linear or interleaved burst sequence. The
interleaved burst order supports Pentium and i486
processors. The linear burst sequence is suited for processors
that utilize a linear burst sequence. The burst order is user
selectable, and is determined by sampling the MODE input.
Accesses can be initiated with either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC).
Address advancement through the burst sequence is
controlled by the ADV input. A two-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW
Enable (GW) overrides all Byte Write inputs and writes data to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE
signals (GW, BWE) are all deserted HIGH. ADSP is ignored if
CE
is stored into the address advancement logic and the address
register while being presented to the memory array. The corre-
sponding data is allowed to propagate to the input of the output
V
V
V
V
MODE
NC
DD
SS
DDQ
SSQ
1
1
Name
is HIGH. The address presented to the address inputs (A)
is HIGH.
1
, CE
2
, CE
15,41,65,
91
17,40,67,
90
4,11,20,
27,54,61,
70,77
5,10,21,
26,55,60,
71,76
31
1,14,16,
30,38,39,
42,43,49,
50,51,66,
80
TQFP
3
are all asserted active, and (3) the Write
(continued)
I/O Power Sup-
Power Supply Power supply inputs to the core of the device.
I/O Ground
Ground
Input-
Static
I/O
ply
[A:D]
) inputs. A Global Write
1
, CE
Ground for the core of the device.
Power supply for the I/O circuitry.
Ground for the I/O circuitry.
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to
V
remain static during device operation. Mode Pin has an internal pull-up.
No Connects. Not internally connected to the die.
DD
2
, CE
or left floating selects interleaved burst sequence. This is a strap pin and should
3
) and an
registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within t
occurs when the SRAM is emerging from a deselected state
to a selected state, its outputs are always three-stated during
the first cycle of the access. After the first cycle of the access,
the outputs are controlled by the OE signal. Consecutive
single Read cycles are supported. Once the SRAM is
deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output will three-state immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and
(2) CE
presented to A is loaded into the address register and the
address advancement logic while being delivered to the
memory array. The Write signals (GW, BWE, and BW
ADV inputs are ignored during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corre-
sponding address location in the memory array. If GW is HIGH,
then the Write operation is controlled by BWE and BW
signals. The CY7C1215F provides Byte Write capability that is
described in the Write Cycle Descriptions table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW
Bytes not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1215F is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ inputs. Doing so will three-state the output drivers.
As a safety precaution, DQs are automatically three-stated
whenever a Write cycle is detected, regardless of the state of
OE.
[A:D]
1
, CE
) input, will selectively write to only the desired bytes.
Description
2
, CE
CO
3
if OE is active LOW. The only exception
are all asserted active. The address
CY7C1215F
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[A:D]
) and
[A:D]