ICS1893CK ICST [Integrated Circuit Systems], ICS1893CK Datasheet - Page 112

• Manufacturer Part Number: ICS1893CK
• Description: 3.3-V 10Base-T/100Base-TX Integrated PHYceive
• Manufacturer: ICST [Integrated Circuit Systems]

9.5.10 100M / MII Media Independent Interface: Transmit Latency
ICS1893CF, Rev. F, 03/01/07
TXEN
TXCLK
TXD
TP_TX
Table 9-17
periods consist of timings of signals on the following pins:
•
•
•
•
Figure 9-11
Table 9-17. MII / 100M Stream Interface Transmit Latency
† The IEEE maximum is 18 bit times.
Figure 9-11. MII / 100M Stream Interface Transmit Latency Timing Diagram
Period
Time
†
unscrambled.
TXEN
TXCLK
TXD (that is, TXD[3:0])
TP_TX (that is, TP_TXP and TP_TXN)
t1
Shown
ICS1893CF Data Sheet - Release
†
TXEN Sampled to MDI Output of First
Bit of /J/ †
lists the significant time periods for the MII / 100 Stream Interface transmit latency. The time
shows the timing diagram for the time periods.
Preamble /J/
Parameter
Copyright © 2007, Integrated Device Technology, Inc.
Preamble /K/
All rights reserved.
t1
112
MII mode
Conditions
Chapter 9 DC and AC Operating Conditions
Min.
–
Typ. Max.
2.8
3
Bit times
Mar. 2007
Units