ICS1893CK ICST [Integrated Circuit Systems], ICS1893CK Datasheet - Page 109
ICS1893CK
Manufacturer Part Number
ICS1893CK
Description
3.3-V 10Base-T/100Base-TX Integrated PHYceive
Manufacturer
ICST [Integrated Circuit Systems]
Datasheet
1.ICS1893CK.pdf
(126 pages)
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9.5.7 MII Management Interface Timing
ICS1893CF, Rev. F, 03/01/07
Table 9-14
timings of signals on the MDC and MDIO pins).
Table 9-14. MII Management Interface Timing
† The ICS1893CF is tested at 25 MHz (a 40-ns period) with a 50-pF load. Designs must account for all board loading
Figure 9-8. MII Management Interface Timing Diagram
MDC
MDIO
(Output)
MDC
MDIO
(Input)
Period
of MDC.
Time
ICS1893CF Data Sheet Rev. F - Release
t1
t2
t3
t4
t5
t6
MDC Minimum High Time
MDC Minimum Low Time
MDC Period
MDC Rise Time to MDIO Valid
MDIO Setup Time to MDC
MDIO Hold Time after MDC
lists the significant time periods for the MII Management Interface timing (which consists of
t1
Parameter
Copyright © 2007, Integrated Device Technology, Inc.
t3
t2
t5
t4
t6
All rights reserved.
109
Figure 9-8
shows the timing diagram for the time periods.
Conditions
Chapter 9 DC and AC Operating Conditions
–
–
–
–
–
–
400†
Min.
160
160
10
10
0
Typ.
–
–
†
–
–
–
Max.
300
–
–
–
–
–
Mar. 2007
Units
ns
ns
ns
ns
ns
ns
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