MT41J128M8 MDTIC [Micon Design Technology Corporation], MT41J128M8 Datasheet - Page 178

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MT41J128M8

Manufacturer Part Number
MT41J128M8
Description
1Gb: x4, x8, x16 DDR3 SDRAM
Manufacturer
MDTIC [Micon Design Technology Corporation]
Datasheet

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Asynchronous to Synchronous ODT Mode Transition (Short CKE Pulse)
PDF: 09005aef826aa906/Source: 09005aef82a357c3
1Gb_DDR3_5.fm - Rev. D 8/1/08 EN
If the time in the precharge power down or idle states is very short (short CKE LOW
pulse), the power-down entry and power-down exit transition periods will overlap.
When overlap occurs, the response of the DRAM’s R
be synchronous or asynchronous from the start of the power-down entry transition
period to the end of the power-down exit transition period even if the entry period ends
later than the exit period (see Figure 122 on page 179).
If the time in the idle state is very short (short CKE HIGH pulse), the power-down exit
and power-down entry transition periods overlap. When this overlap occurs, the
response of the DRAM’s R
chronous from the start of power-down exit transition period to the end of the power-
down entry transition period (see Figure 122 on page 179).
TT
to a change in the ODT state may be synchronous or asyn-
178
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
TT
to a change in the ODT state may
On-Die Termination (ODT)
©2006 Micron Technology, Inc. All rights reserved.

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