CY7C0852V CYPRESS [Cypress Semiconductor], CY7C0852V Datasheet - Page 18

• Manufacturer Part Number: CY7C0852V
• Description: FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06070 Rev. *D
Switching Waveforms
Bank Select Read
Notes:
26. In this depth-expansion example, B1 represents Bank #1 and B2 is Bank #2; each bank consists of one Cypress CY7C0851V/CY7C0852V device from this data
27.
28. Output state (HIGH, LOW, or high-impedance) is determined by the previous cycle control signals.
29. During “No Operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
30.
31. CE
ADDRESS
ADDRESS
Read-to-Write-to-Read (OE = LOW)
DATA
DATA
ADDRESS
DATA
sheet. ADDRESS
completed (labelled as no operation). One clock cycle is required to three-state the I/O for the Write operation on the next rising edge of CLK.
DATA
ADS = CNTEN= B0 – B3 = OE = LOW; MRST = CNTRST = CNT/MSK = HIGH.
CE
OUT(B2)
0
OUT(B1)
0
CE
CE
CLK
R/W
= B0 – B3 = R/W = LOW; CE
OUT
= OE = B0 – B3 = LOW; CE
CE
CLK
IN
(B1)
(B1)
(B2)
(B2)
t
t
t
SW
SC
SA
t
t
t
t
SA
SC
SA
SC
(B1)
[26, 27]
= ADDRESS
A
n
A
A
0
t
0
CH2
t
CH2
t
(continued)
t
CYC2
1
t
t
1
HW
HC
HA
(B2)
= R/W = CNTRST = MRST = HIGH.
t
t
t
= CNTRST = MRST = CNT/MSK = HIGH. When R/W first switches low, since OE = LOW, the Write operation cannot be
t
t
CYC2
HA
HC
HA
HC
.
t
CL2
t
CL2
[25, 28, 29, 30, 31]
A
READ
n+1
A
A
t
CD2
1
1
t
CD2
t
SW
t
Q
SC
n
Q
t
A
0
SC
n+2
t
A
CKHZ
NO OPERATION
A
2
2
t
t
DC
HC
t
HW
t
HC
t
CD2
t
SD
A
D
n+2
n+2
Q
t
A
A
HD
1
3
t
3
DC
t
t
CKLZ
CKHZ
WRITE
t
CD2
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
A
n+3
Q
A
A
4
4
2
t
t
t
CKHZ
CD2
CKLZ
READ
t
CKLZ
Q
3
A
n+4
Page 18 of 29
A
t
A
CD2
5
t
5
CKLZ
t
t
CKHZ
CD2
Q
n+3
Q
4