CY7C0852V CYPRESS [Cypress Semiconductor], CY7C0852V Datasheet - Page 11

• Manufacturer Part Number: CY7C0852V
• Description: FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-06070 Rev. *D
IEEE 1149.1 Serial Boundary Scan (JTAG)
The
incorporates an IEEE 1149.1 serial boundary scan test access
port (TAP). The TAP controller functions in a manner that does
not conflict with the operation of other devices using
1149.1-compliant
JEDEC-standard 3.3V I/O logic levels. It is composed of three
input connections and one output connection required by the
test logic defined by the standard.
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are
Table 4. Identification Register Definitions
Revision Number (31:28)
Cypress Device ID (27:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
Notes:
12. The “X” in this diagram represents the counter upper bits.
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance
Instruction Field
CY7C0850V/CY7C0851V/CY7C0852V/CY7C0853V
TAPs.
Example:
Load
Counter-Mask
Register = 3F
Load
Address
Counter = 8
Max + 1
Address
Register
Max
Address
Register
The
Figure 2. Programmable Counter-Mask Register Operation
0h
C001h
C002h
C092h
034h
1
TAP
Value
CNTINT
H
H
L
H
operates
DD
) for five rising
2
2
2
2
Allows unique identification of the DP family device vendor.
Reserved for version number.
Defines Cypress part number for the CY7C0851V
Defines Cypress part number for the CY7C0852V and CY7C0853V
Defines Cypress part number for the CY7C0850V
Indicates the presence of an ID register.
16
16
16
16
X
0
X
X
2
2
2
2
15
15
15
15
X
0
X
X
[13]
Masked Address
using
Xs
0s
Xs
Xs
operating. An MRST must be performed on the devices after
power-up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the
scan chain will output the next bit in the chain twice. For
example, if the value expected from the chain is 1010101, the
device will output a 11010101. This extra bit will cause some
testers to report an erroneous failure for the devices in a scan
test. Therefore the tester should be configured to never enter
the PAUSE-DR state.
.
2
2
2
2
6
6
6
6
X
0
X
X
2
2
2
2
5
5
5
5
0 0
1 1
0 0
1 1
Description
Unmasked Address
2
2
2
2
4
4
4
4
2
2
2
2
CY7C0850V/CY7C0851V
CY7C0852V/CY7C0853V
3
3
3
3
1
1
1
1
2
2
2
2
2
2
2
2
0
1
0
1
[1, 12]
2
2
2
2
1
1
1
1
0
1
0
1
2
2
2
2
0
0
0
0
0
1
0
1
Mask
Register
bit-0
Address
Counter
bit-0
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