CY7C024-25JI CYPRESS [Cypress Semiconductor], CY7C024-25JI Datasheet - Page 13

• Manufacturer Part Number: CY7C024-25JI
• Description: 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Busy Timing Diagram No.2 (Address Arbitration)
Left Address Valid First
Document #: 38-06035 Rev. *B
Busy Timing Diagram No.1 (CE Arbitration)
CE
CE
Right Address Valid First:
Note:
38. If t
L
ADDRESS
ADDRESS
R
Valid First:
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
PS
BUSY
BUSY
BUSY
BUSY
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted.
CE
CE
CE
CE
L,R
L,R
R
R
R
L
R
L
L
L
R
R
L
L
(continued)
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
t
t
RC
RC
or t
or t
t
t
PS
PS
WC
WC
[38]
t
t
BLA
BLA
[38]
ADDRESS MATCH
ADDRESS MATCH
t
t
BLC
BLC
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C024/0241
CY7C025/0251
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