CY7C024-15JXC Cypress Semiconductor Corp, CY7C024-15JXC Datasheet
CY7C024-15JXC
Specifications of CY7C024-15JXC
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CY7C024-15JXC Summary of contents
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... CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/ 0241 and CY7C025/0251 can be used as standalone 16 or 18-bit dual-port static RAMs or multiple devices can be combined to function as a 32-/36-bit or wider master/ slave dual-port static RAM ...
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... Notes 2. BUSY is an output in master mode and an input in slave mode. 3. I/O –I/O on the CY7C0241/0251 I/O –I/O on the CY7C0241/0251 the CY7C025/0251. 12L the CY7C025/0251. 12R Document #: 38-06035 Rev. *D I/O I/O CONTROL CONTROL MEMORY ADDRESS ADDRESS ARRAY DECODER DECODER ...
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... Figure 2. 100-Pin TQFP (Top View CY7C024 Chip Enable Read/Write Enable Output Enable Address Data Bus Input/Output Semaphore Enable Upper Byte Select Lower Byte Select Interrupt Flag Busy Flag Master or Slave Select Power Ground CY7C024/024A/0241 CY7C025/0251 INT 65 L BUSY L 64 GND 63 M/S 62 ...
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... CY7C024/024A/0241, 1FFF for the CY7C025/0251) is the mailbox for the right port and the second-highest memory location (FFE for the CY7C024/024A/0241, 1FFE for the CY7C025/0251) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner ...
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... [ [ (1)FFE H CY7C024/024A/0241 CY7C025/0251 Table 3 shows sample semaphore operations. of each other, the semaphore is SPS Operation [4] 15 Deselected: Power Down Deselected: Power Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only ...
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... Right port obtains semaphore token change. Left port has no write access to semaphore 0 1 Left port obtains semaphore token 1 1 Semaphore-free 1 0 Right port has semaphore token 1 1 Semaphore-free 0 1 Left port has semaphore token 1 1 Semaphore-free CY7C024/024A/0241 CY7C025/0251 Status Page [+] Feedback ...
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... Test Conditions Min = Min –4 Min 4 –0.7 ≤ V – ≤ V – CY7C024/024A/0241 CY7C025/0251 [11] ........................................–0.5V to +7.0V Ambient Temperature ± 10% 0°C to +70°C 5V ± 10% –40°C to +85°C 7C024/024A/0241–25 7C025/0251–25 Typ Max Min Typ Max 2.4 0.4 0.4 2 ...
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... Figure 3. AC Test Loads and Waveforms R = 250Ω TH OUTPUT C = 30pF V = 1.4V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 90% 90% 10% 10% ≤ ≤ CY7C024/024A/0241 CY7C025/0251 7C024/024A/0241–55 7C025/0251–35 7C025/0251–55 Typ Max Min Typ Max 160 230 150 230 160 260 150 260 30 ...
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... Document #: 38-06035 Rev. *D [14] 7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C025/0251–15 7C025/0251–25 Min Max Min Max less than t and t is less than t HZCE LZCE HZOE Figure 11. CY7C024/024A/0241 CY7C025/0251 7C024/024A/0241–55 7C025/0251–35 7C025/0251–55 Unit Min Max Min Max ...
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... SPS t SEM Address Access Time SAA Data Retention Mode The CY7C024/024A/0241 is designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within – ...
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... Document #: 38-06035 Rev DATA VALID t ACE t DOE t LZOE t LZCE [23, 25, 26, 26, 27 LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C024/024A/0241 CY7C025/0251 [23, 24, 25] t OHA [23, 26, 27] t HZCE t HZOE DATA VALID OHA t HZCE t HZCE Page [+] Feedback ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06035 Rev [31] t PWE [34] t HZWE SCE PWE HZWE . IH . CY7C024/024A/0241 CY7C025/0251 [28, 29, 30, 31] [34] t HZOE LZWE NOTE [28, 29, 30, 36 allow the I/O drivers to turn off and data Page [+] Feedback ...
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... SPS Document #: 38-06035 Rev VALID ADRESS SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE MATCH t SPS MATCH = HIGH. L CY7C024/024A/0241 CY7C025/0251 [37] t OHA t ACE DATA VALID OUT t DOE [38, 39, 40] Page [+] Feedback ...
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... Figure 11. Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Figure 12. Write Timing with Busy Input (M/S=LOW) R/W BUSY Note 41 LOW L R Document #: 38-06035 Rev MATCH t PWE t SD VALID MATCH t BLA t WDD t PWE CY7C024/024A/0241 CY7C025/0251 [41 BHA t BDD t DDD VALID Page [+] Feedback ...
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... BUSY is asserted. PS Document #: 38-06035 Rev. *D ADDRESS MATCH BLC ADDRESS MATCH BLC ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA CY7C024/024A/0241 CY7C025/0251 [42] t BHC t BHC [42] Page [+] Feedback ...
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... R deasserted first 44 depends on which enable pin (CE or R/W INS INR L Document #: 38-06035 Rev. *D Figure 15. Interrupt Timing Diagrams t WC [43 (1FFF CY7C025) [44] t INR t WC [43 READ FFE (1FFE CY7C025) [44] t INR ) is asserted last. L CY7C024/024A/0241 CY7C025/0251 t RC READ FFF t RC Page [+] Feedback ...
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... Ordering Information 4K x16 Dual-Port SRAM) ( Speed (ns) Ordering Code 15 CY7C024–15AC CY7C024-15AXC CY7C024–15JC CY7C024-15JXC 25 CY7C024–25AC CY7C024-25AXC CY7C024–25JC CY7C024A-25JXC CY7C024–25AI CY7C024-25AXI CY7C024–25JI CY7C024-25JXI 35 CY7C024–35AC CY7C024-35AXC CY7C024–35JC CY7C024-35JXC CY7C024–35AI CY7C024-35AXI CY7C024–35JI CY7C024-35JXI 55 CY7C024–55AC CY7C024-55AXC CY7C024– ...
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... Ordering Code 15 CY7C0241–15AC CY7C0241-15AXC CY7C0241–15AI CY7C0241-15AXI 25 CY7C0241–25AC CY7C0241-25AXC CY7C0241–25AI CY7C0241-25AXI 35 CY7C0241–35AC CY7C0241-35AXC CY7C0241–35AI CY7C0241-35AXI Document #: 38-06035 Rev. *D (continued) Package Name Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb Free Thin Quad Flat Pack J83 ...
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... Pb Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb Free Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Pb Free Thin Quad Flat Pack CY7C024/024A/0241 CY7C025/0251 Operating Range Commercial Industrial Operating Range Commercial ...
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... Package Diagrams Figure 16. 100-Pin Pb-Free Thin Plastic Quad Flat Pack (TQFP) A100 Figure 17. 84-Pin Pb Free Plastic Leaded Chip Carrier J83 Document #: 38-06035 Rev. *D CY7C024/024A/0241 CY7C025/0251 51-85048-*C 51-85006-*A Page [+] Feedback ...
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... Document History Page Document Title: CY7C024/024A/0241, CY7C025/0251 4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with Sem, Int, Busy Document Number: 38-06035 Orig. of Submission Rev. ECN No. Change ** 110177 SZV 09/29/01 *A 122286 RBI *B 236754 YDT See ECN *C 279132 RUY See ECN *D 2623540 ...