CY7C0241 CYPRESS [Cypress Semiconductor], CY7C0241 Datasheet - Page 2
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CY7C0241
Manufacturer Part Number
CY7C0241
Description
4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY
Manufacturer
CYPRESS [Cypress Semiconductor]
Datasheet
1.CY7C0241.pdf
(21 pages)
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Document #: 38-06035 Rev. *C
Pin Configurations
Notes:
Logic Block Diagram
1. BUSY is an output in master mode and an input in slave mode.
2. I/O
3. I/O
4. A
5. A
12L
12R
0
9
–I/O
–I/O
on the CY7C025/0251.
on the CY7C025/0251.
8
17
on the CY7C0241/0251.
on the CY7C0241/0251.
(CY7C025/0251)
I/O
I/O
8L
0L
OE
– I/O
– I/O
I/O
I/O
I/O
I/O
I/O
I/O
L
BUSY
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L
I/O
I/O
GND
GND
L
L
V
V
10L
11L
12L
13L
14L
15L
CC
CC
0R
1R
2R
3R
4R
5R
6R
7R
8R
15L
7L
8L
9L
[2]
L
A
A
[3]
A
[1]
12L
11L
0L
R/W
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
32
SEM
28
29
30
31
INT
L
33
L
11
L
34
10
35
9
36
ADDRESS
DECODER
8
37
7
38
6
CE
OE
UB
LB
39
CONTROL
5
L
L
L
L
40
I/O
4
41
84-Pin PLCC
3
42
CY7C024/5
Top View
2
43
SEMAPHORE
ARBITRATION
1
INTERRUPT
44
MEMORY
ARRAY
84
M/S
45
83
46
82
47
81
48
CONTROL
80
49
I/O
79
50
78
CE
OE
UB
LB
ADDRESS
DECODER
51
R
R
R
R
77
52
76
53
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
A
A
A
A
A
A
A
INT
BUSY
GND
M/S
BUSY
A
A
A
A
A
A
A
INT
INT
A
7L
6L
5L
4L
3L
2L
1L
0R
1R
2R
3R
4R
5R
6R
SEM
0L
R/W
R
L
R
L
R
R
R
A
A
A
I/O
I/O
BUSY
12R
11R
0R
8R
0R
R/W
(CY7C025/0251)
OE
–
–
UB
LB
R
I/O
I/O
[1]
CE
R
R
R
R
15R
7R
R
CY7C024/0241
CY7C025/0251
[3]
[2]
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