CY7C006-15JC CYPRESS [Cypress Semiconductor], CY7C006-15JC Datasheet - Page 11

• Manufacturer Part Number: CY7C006-15JC
• Description: 16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Waveforms
Busy Timing Diagram No. 1 (CE Arbitration)
CE
CE
Left AddressValid First:
Right Address Valid First:
Busy Timing Diagram No. 2 (Address Arbitration)
Notes:
29. If t
30. t
31. t
ADDRESS
ADDRESS
L
R
ADDRESS
ADDRESS
ADDRESS
ADDRESS
Valid First:
Valid First:
HA
INS
PS
BUSY
BUSY
depends on which enable pin (CE
BUSY
or t
BUSY
is violated, the busy signal will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
CE
CE
CE
CE
INR
L,R
L,R
R
R
L
L
depends on which enable pin (CE
R
L
R
R
R
L
L
L
(continued)
L
or R/W
t
t
PS
PS
ADDRESS MATCH
ADDRESS MATCH
L
L
or R/W
) is deasserted first.
t
t
RC
RC
or t
or t
L
t
t
PS
PS
) is asserted last.
WC
WC
t
t
[29]
BLA
BLA
ADDRESS MATCH
ADDRESS MATCH
[28]
t
t
BLC
BLC
11
ADDRESS MISMATCH
ADDRESS MISMATCH
t
t
BHA
BHA
t
t
BHC
BHC
CY7C006
CY7C016
C006-19
C006-20
C006-21
C006-22