SCA21X0 VTI [VTI technologies], SCA21X0 Datasheet - Page 20

• Manufacturer Part Number: SCA21X0
• Description: VTI Automotive Digital Accelerometer Platform
• Manufacturer: VTI [VTI technologies]

4
VTI Technologies Oy
www.vti.fi
SPI Interface
Serial peripheral interface (SPI) is a 4-wire synchronous serial interface. Data communication is
enabled with active low Slave Select or Chip Select wire (CSB). Data is transmitted via 3-wire
interface consisting of serial data input (MOSI), serial data output (MISO) and serial clock (SCK).
Every SPI system consists of one master and one or more slaves, where the master is defined as
the microcomputer that provides the SPI clock, and the slave is any integrated circuit that receives
the SPI clock from the master.
Figure 2: Typical SPI connection
The SPI interface of VTI automotive series is designed to support almost any micro controller that
uses software implemented SPI. However it is not designed to support any particular hardware
implemented SPI found in many commercial micro controllers. SCA8X0/SCA21X0/SCA31X0
accelerometer operates always as a slave device in the master-slave operation mode. The data
transfer between the master (µP test machine etc.) and accelerometer is performed serially with
four wire system.
Each transmission starts with a falling edge on CSB and ends with the rising edge. During the
transmission, commands and data are controlled by SCK and CSB according to the following rules:
SPI
SCA8X0/SCA21X0/SCA31X0. Registers can be read and write.
SPI communication is full duplex communication. Data is send and received simultaneously.
MOSI
MISO
SCK
CSB
•
•
•
communication
commands and data are shifted MSB first LSB last
each output data/status-bits are shifted out on the falling edge of SCK (MISO line)
each bit is sampled on the rising edge of SCK (MOSI line)
MASTER
MICROCONTROLLER
SERIAL CLK (SCK)
DATA OUT (MOSI)
DATA IN (MISO)
transfers
CSB3
CSB0
CSB1
CSB2
master out slave in
master in slave out
serial clock
chip select (low active)
Doc. Nr. 82 694 00 C
data
between
MOSI
MISO
SCK
CSB
MOSI
MISO
SCK
CSB
MOSI
MISO
SCK
CSB
MOSI
MISO
SCK
CSB
SPI
SLAVE
master
and
µP → ASIC
ASIC → µP
µP → ASIC
µP → ASIC
SCA8X0/21X0/3100 Series
registers
of
20/35
the