LTC4110EUHF LINER [Linear Technology], LTC4110EUHF Datasheet - Page 6

• Manufacturer Part Number: LTC4110EUHF
• Description: Battery Backup System Manager
• Manufacturer: LINER [Linear Technology]

LTC4110
ELECTRICAL CHARACTERISTICS
SYMBOL
V
Logic and Status Output Levels
V
V
V
V
I
V
V
V
V
I
T
SMBus Timing (Note 9)
t
t
t
t
t
t
t
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime. Specifi c functionality or parametric performance
of the device beyond the limits expressly given in the Electrical
Characteristics table is not implied by these maximum ratings.
Note 2: The LTC4110E is guaranteed to meet performance specifi cations
from 0°C to 85°C. Specifi cations over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions.
Overtemperature protection will become active at a junction temperature
greater than the maximum operating junction temperature. Continuous
operation above the specifi ed maximum operation temperature may result
in device degradation or failure. Operating junction temperature T
°C) is calculated from the ambient temperature T
dissipation P
6
temperature range, otherwise specifi cations are at T
GND = SGND = CLP = CLN = SHDN = 0V and R
are negative. All voltages are referenced to GND, unless otherwise specifi ed.
OHG
ISD
HIGH
LOW
TO
F
SU-STA
HD-STA
HD-DAT
LR
REMH
ILS
IHS
OLS
OLG
ILG
IHG
ILSD
IHSD
D
PARAMETER
THB Pin Battery Removal Threshold
Hysteresis Voltage
SCL/SDA Input Pins Low Voltage
SCL/SDA Input Pins High Voltage
SDA Output Pin Low Voltage
ACPb, GPIO1,2,3 Output Pins Low Voltage
ACPb, GPIO1,2,3 Output Pins Open
Leakage Current
GPIO Input Low Voltage
GPIO Input High Voltage
SHDN Input Pin Low Voltage
SHDN Input Pin High Voltage
SHDN Input Pin Pull-Up Current
Logic Reset Duration After Power-Up
From Zero
SCL Serial Clock High Period
SCL Serial Clock Low Period
Timeout Period
SDA/SCL Fall Time
Start Condition Set-Up Time
Start Condition Hold Time
SDA to SCL Falling-Edge Hold Time,
Slave Clocking in Data
(in watts) by the formula T
J
= T
A
+ θ
A
and the average power
JA
VREF
• P
D
.
= 49.9k. All currents into device pins are positive and all currents out of device pins
A
= 25°C. Unless otherwise specifi ed, V
CONDITIONS
V
I
I
Outputs Open, V
V
V
V
I
R
I
R
C
PULL-UP
ACPb
PULL-UP
PULL-UP
THB
SHDN
DCIN
BAT
LOAD
PU
PU
J
(in
= 9.31k
= 9.31k
, I
Decreasing; Lead Acid Only
= 0
The
Transition From 0V to 5V in <1ms;
= 250pF , R
= 2.4V
GPIO1
= 350μA
= 350μA, C
= 350μA, C
l
, I
denotes the specifi cations which apply over the full operating
GPIO2
ACPb
PU
Note 4: The LTC4110 is idle with no application load. It is not charging
or calibrating the battery and is not in backup or shutdown mode. The
internal clock is running and the SMBus is functional.
Note 5: Combined current of CSP , CSN and BAT pins set to V
application load.
Note 6: C
SafetySignal.
Note 7: Does not include tolerance of current sense or current
programming resistors.
Note 8: Given as a per cell voltage referred to the BAT pin (V
series cells).
Note 9: Refer to System Management Bus Specifi cation, Revision 1.1,
section 2.1 for Timing Diagrams and section 8.1, for t
requirements.
Note 10: Specifi cations over the –5°C to 85°C operating ambient
temperature range are assured by design, characterization and correlation
with statistical process controls.
, I
LOAD
LOAD
= 9.31k
, V
GPIO3
GPIO1,2,3
= 250pF ,
= 250pF ,
TH
= 10mA
is defi ned as the sum of capacitance on THA, THB
= 5V
DCIN
l
l
l
l
l
l
l
l
l
l
l
l
= V
DCOUT
MIN
–3.5
300
2.1
1.5
2.4
4.7
4.7
–2
25
4
4
= V
DCDIV
TYP
25
–2
= 12V, V
LOW
MAX
300
and t
0.8
0.4
0.5
–1
1
2
1
1
BAT
BAT
BAT
TIMEOUT
/number of
with no
= 8.4V,
UNITS
4110fa
mV
ms
μA
μA
μs
μs
ns
μs
μs
ns
V
V
V
V
V
V
V
V
s